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Documentation / devicetree / bindings / sound / samsung-i2s.txt

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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Samsung I2S controller
3	Required SoC Specific Properties:
5	- compatible : should be one of the following.
6	   - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
7	   - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
8	     secondary fifo, s/w reset control and internal mux for root clk src.
9	   - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
10	     playback, sterio channel capture, secondary fifo using internal
11	     or external dma, s/w reset control, internal mux for root clk src
12	     and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
13	     is to allow transfer of multiple channel audio data on single data line.
14	   - samsung,exynos7-i2s: with all the available features of exynos5 i2s,
15	     exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo
16	     with only external dma and more no.of root clk sampling frequencies.
17	   - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
18	     stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with
19	     slightly modified bit offsets.
21	- reg: physical base address of the controller and length of memory mapped
22	  region.
23	- dmas: list of DMA controller phandle and DMA request line ordered pairs.
24	- dma-names: identifier string for each DMA request line in the dmas property.
25	  These strings correspond 1:1 with the ordered pairs in dmas.
26	- clocks: Handle to iis clock and RCLK source clk.
27	- clock-names:
28	  i2s0 uses some base clks from CMU and some are from audio subsystem internal
29	  clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
30	  "i2s_opclk1" as shown in the example below.
31	  i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
32	  be "iis" and "i2s_opclk0".
33	  "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
34	  clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
35	  doesn't have any such mux.
36	- #clock-cells: should be 1, this property must be present if the I2S device
37	  is a clock provider in terms of the common clock bindings, described in
38	  ../clock/clock-bindings.txt.
39	- clock-output-names: from the common clock bindings, names of the CDCLK
40	  I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
41	  "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively.
43	There are following clocks available at the I2S device nodes:
44	 CLK_I2S_CDCLK    - the CDCLK (CODECLKO) gate clock,
45	 CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the
46			    IISPSR register),
47	 CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in
48			    IISMOD register).
50	Refer to the SoC datasheet for availability of the above clocks.
51	The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
52	in the IIS Multi Audio Interface (I2S0).
53	Note: Old DTs may not have the #clock-cells, clock-output-names properties
54	and then not use the I2S node as a clock supplier.
56	Optional SoC Specific Properties:
58	- samsung,idma-addr: Internal DMA register base address of the audio
59	  sub system(used in secondary sound source).
60	- pinctrl-0: Should specify pin control groups used for this controller.
61	- pinctrl-names: Should contain only one value - "default".
64	Example:
66	i2s0: i2s@03830000 {
67		compatible = "samsung,s5pv210-i2s";
68		reg = <0x03830000 0x100>;
69		dmas = <&pdma0 10
70			&pdma0 9
71			&pdma0 8>;
72		dma-names = "tx", "rx", "tx-sec";
73		clocks = <&clock_audss EXYNOS_I2S_BUS>,
74			<&clock_audss EXYNOS_I2S_BUS>,
75			<&clock_audss EXYNOS_SCLK_I2S>;
76		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
77		#clock-cells;
78		clock-output-names = "i2s_cdclk0";
79		samsung,idma-addr = <0x03000000>;
80		pinctrl-names = "default";
81		pinctrl-0 = <&i2s0_bus>;
82	};
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