Based on kernel version 3.17.3. Page generated on 2014-11-14 22:16 EST.
1 Device-Tree bindings for LVDS Display Bridge (ldb) 2 3 LVDS Display Bridge 4 =================== 5 6 The LVDS Display Bridge device tree node contains up to two lvds-channel 7 nodes describing each of the two LVDS encoder channels of the bridge. 8 9 Required properties: 10 - #address-cells : should be <1> 11 - #size-cells : should be <0> 12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". 13 Both LDB versions are similar, but i.MX6 has an additional 14 multiplexer in the front to select any of the four IPU display 15 interfaces as input for each LVDS channel. 16 - gpr : should be <&gpr> on i.MX53 and i.MX6q. 17 The phandle points to the iomuxc-gpr region containing the LVDS 18 control register. 19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to 20 the display interface selector clocks, as described in 21 Documentation/devicetree/bindings/clock/clock-bindings.txt 22 The following clocks are expected on i.MX53: 23 "di0_pll" - LDB LVDS channel 0 mux 24 "di1_pll" - LDB LVDS channel 1 mux 25 "di0" - LDB LVDS channel 0 gate 26 "di1" - LDB LVDS channel 1 gate 27 "di0_sel" - IPU1 DI0 mux 28 "di1_sel" - IPU1 DI1 mux 29 On i.MX6q the following additional clocks are needed: 30 "di2_sel" - IPU2 DI0 mux 31 "di3_sel" - IPU2 DI1 mux 32 The needed clock numbers for each are documented in 33 Documentation/devicetree/bindings/clock/imx5-clock.txt, and in 34 Documentation/devicetree/bindings/clock/imx6q-clock.txt. 35 36 Optional properties: 37 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q 38 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, 39 not used on i.MX6q 40 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should 41 be configured - one input will be distributed on both outputs in dual 42 channel mode 43 44 LVDS Channel 45 ============ 46 47 Each LVDS Channel has to contain a display-timings node that describes the 48 video timings for the connected LVDS display. For detailed information, also 49 have a look at Documentation/devicetree/bindings/video/display-timing.txt. 50 51 Required properties: 52 - reg : should be <0> or <1> 53 - fsl,data-mapping : should be "spwg" or "jeida" 54 This describes how the color bits are laid out in the 55 serialized LVDS signal. 56 - fsl,data-width : should be <18> or <24> 57 - port: A port node with endpoint definitions as defined in 58 Documentation/devicetree/bindings/media/video-interfaces.txt. 59 On i.MX5, the internal two-input-multiplexer is used. 60 Due to hardware limitations, only one port (port@[0,1]) 61 can be used for each channel (lvds-channel@[0,1], respectively) 62 On i.MX6, there should be four ports (port@[0-3]) that correspond 63 to the four LVDS multiplexer inputs. 64 65 example: 66 67 gpr: iomuxc-gpr@53fa8000 { 68 /* ... */ 69 }; 70 71 ldb: ldb@53fa8008 { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 compatible = "fsl,imx53-ldb"; 75 gpr = <&gpr>; 76 clocks = <&clks 122>, <&clks 120>, 77 <&clks 115>, <&clks 116>, 78 <&clks 123>, <&clks 85>; 79 clock-names = "di0_pll", "di1_pll", 80 "di0_sel", "di1_sel", 81 "di0", "di1"; 82 83 lvds-channel@0 { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 reg = <0>; 87 fsl,data-mapping = "spwg"; 88 fsl,data-width = <24>; 89 90 display-timings { 91 /* ... */ 92 }; 93 94 port@0 { 95 reg = <0>; 96 97 lvds0_in: endpoint { 98 remote-endpoint = <&ipu_di0_lvds0>; 99 }; 100 }; 101 }; 102 103 lvds-channel@1 { 104 #address-cells = <1>; 105 #size-cells = <0>; 106 reg = <1>; 107 fsl,data-mapping = "spwg"; 108 fsl,data-width = <24>; 109 110 display-timings { 111 /* ... */ 112 }; 113 114 port@1 { 115 reg = <1>; 116 117 lvds1_in: endpoint { 118 remote-endpoint = <&ipu_di1_lvds1>; 119 }; 120 }; 121 }; 122 };