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Based on kernel version 4.16.1. Page generated on 2018-04-09 11:53 EST.

2	-------
3	PHY Abstraction Layer
4	(Updated 2008-04-08)
6	Purpose
8	 Most network devices consist of set of registers which provide an interface
9	 to a MAC layer, which communicates with the physical connection through a
10	 PHY.  The PHY concerns itself with negotiating link parameters with the link
11	 partner on the other side of the network connection (typically, an ethernet
12	 cable), and provides a register interface to allow drivers to determine what
13	 settings were chosen, and to configure what settings are allowed.
15	 While these devices are distinct from the network devices, and conform to a
16	 standard layout for the registers, it has been common practice to integrate
17	 the PHY management code with the network driver.  This has resulted in large
18	 amounts of redundant code.  Also, on embedded systems with multiple (and
19	 sometimes quite different) ethernet controllers connected to the same 
20	 management bus, it is difficult to ensure safe use of the bus.
22	 Since the PHYs are devices, and the management busses through which they are
23	 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
24	 In doing so, it has these goals:
26	   1) Increase code-reuse
27	   2) Increase overall code-maintainability
28	   3) Speed development time for new network drivers, and for new systems
30	 Basically, this layer is meant to provide an interface to PHY devices which
31	 allows network driver writers to write as little code as possible, while
32	 still providing a full feature set.
34	The MDIO bus
36	 Most network devices are connected to a PHY by means of a management bus.
37	 Different devices use different busses (though some share common interfaces).
38	 In order to take advantage of the PAL, each bus interface needs to be
39	 registered as a distinct device.
41	 1) read and write functions must be implemented.  Their prototypes are:
43	     int write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
44	     int read(struct mii_bus *bus, int mii_id, int regnum);
46	   mii_id is the address on the bus for the PHY, and regnum is the register
47	   number.  These functions are guaranteed not to be called from interrupt
48	   time, so it is safe for them to block, waiting for an interrupt to signal
49	   the operation is complete
51	 2) A reset function is optional.  This is used to return the bus to an
52	   initialized state.
54	 3) A probe function is needed.  This function should set up anything the bus
55	   driver needs, setup the mii_bus structure, and register with the PAL using
56	   mdiobus_register.  Similarly, there's a remove function to undo all of
57	   that (use mdiobus_unregister).
59	 4) Like any driver, the device_driver structure must be configured, and init
60	   exit functions are used to register the driver.
62	 5) The bus must also be declared somewhere as a device, and registered.
64	 As an example for how one driver implemented an mdio bus driver, see
65	 drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file
66	 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
68	(RG)MII/electrical interface considerations
70	 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
71	 electrical signal interface using a synchronous 125Mhz clock signal and several
72	 data lines. Due to this design decision, a 1.5ns to 2ns delay must be added
73	 between the clock line (RXC or TXC) and the data lines to let the PHY (clock
74	 sink) have enough setup and hold times to sample the data lines correctly. The
75	 PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
76	 the PHY driver and optionally the MAC driver, implement the required delay. The
77	 values of phy_interface_t must be understood from the perspective of the PHY
78	 device itself, leading to the following:
80	 * PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any
81	   internal delay by itself, it assumes that either the Ethernet MAC (if capable
82	   or the PCB traces) insert the correct 1.5-2ns delay
84	 * PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay
85	   for the transmit data lines (TXD[3:0]) processed by the PHY device
87	 * PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay
88	   for the receive data lines (RXD[3:0]) processed by the PHY device
90	 * PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for
91	   both transmit AND receive data lines from/to the PHY device
93	 Whenever possible, use the PHY side RGMII delay for these reasons:
95	 * PHY devices may offer sub-nanosecond granularity in how they allow a
96	   receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
97	   precision may be required to account for differences in PCB trace lengths
99	 * PHY devices are typically qualified for a large range of applications
100	   (industrial, medical, automotive...), and they provide a constant and
101	   reliable delay across temperature/pressure/voltage ranges
103	 * PHY device drivers in PHYLIB being reusable by nature, being able to
104	   configure correctly a specified delay enables more designs with similar delay
105	   requirements to be operate correctly
107	 For cases where the PHY is not capable of providing this delay, but the
108	 Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
109	 should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be
110	 configured correctly in order to provide the required transmit and/or receive
111	 side delay from the perspective of the PHY device. Conversely, if the Ethernet
112	 MAC driver looks at the phy_interface_t value, for any other mode but
113	 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
114	 disabled.
116	 In case neither the Ethernet MAC, nor the PHY are capable of providing the
117	 required delays, as defined per the RGMII standard, several options may be
118	 available:
120	 * Some SoCs may offer a pin pad/mux/controller capable of configuring a given
121	   set of pins'strength, delays, and voltage; and it may be a suitable
122	   option to insert the expected 2ns RGMII delay.
124	 * Modifying the PCB design to include a fixed delay (e.g: using a specifically
125	   designed serpentine), which may not require software configuration at all.
127	Common problems with RGMII delay mismatch
129	 When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
130	 will most likely result in the clock and data line signals to be unstable when
131	 the PHY or MAC take a snapshot of these signals to translate them into logical
132	 1 or 0 states and reconstruct the data being transmitted/received. Typical
133	 symptoms include:
135	 * Transmission/reception partially works, and there is frequent or occasional
136	   packet loss observed
138	 * Ethernet MAC may report some or all packets ingressing with a FCS/CRC error,
139	   or just discard them all
141	 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
142	   (since there is enough setup/hold time in that case)
145	Connecting to a PHY
147	 Sometime during startup, the network driver needs to establish a connection
148	 between the PHY device, and the network device.  At this time, the PHY's bus
149	 and drivers need to all have been loaded, so it is ready for the connection.
150	 At this point, there are several ways to connect to the PHY:
152	 1) The PAL handles everything, and only calls the network driver when
153	   the link state changes, so it can react.
155	 2) The PAL handles everything except interrupts (usually because the
156	   controller has the interrupt registers).
158	 3) The PAL handles everything, but checks in with the driver every second,
159	   allowing the network driver to react first to any changes before the PAL
160	   does.
162	 4) The PAL serves only as a library of functions, with the network device
163	   manually calling functions to update status, and configure the PHY
166	Letting the PHY Abstraction Layer do Everything
168	 If you choose option 1 (The hope is that every driver can, but to still be
169	 useful to drivers that can't), connecting to the PHY is simple:
171	 First, you need a function to react to changes in the link state.  This
172	 function follows this protocol:
174	   static void adjust_link(struct net_device *dev);
176	 Next, you need to know the device name of the PHY connected to this device. 
177	 The name will look something like, "0:00", where the first number is the
178	 bus id, and the second is the PHY's address on that bus.  Typically,
179	 the bus is responsible for making its ID unique.
181	 Now, to connect, just call this function:
183	   phydev = phy_connect(dev, phy_name, &adjust_link, interface);
185	 phydev is a pointer to the phy_device structure which represents the PHY.  If
186	 phy_connect is successful, it will return the pointer.  dev, here, is the
187	 pointer to your net_device.  Once done, this function will have started the
188	 PHY's software state machine, and registered for the PHY's interrupt, if it
189	 has one.  The phydev structure will be populated with information about the
190	 current state, though the PHY will not yet be truly operational at this
191	 point.
193	 PHY-specific flags should be set in phydev->dev_flags prior to the call
194	 to phy_connect() such that the underlying PHY driver can check for flags
195	 and perform specific operations based on them.
196	 This is useful if the system has put hardware restrictions on
197	 the PHY/controller, of which the PHY needs to be aware.
199	 interface is a u32 which specifies the connection type used
200	 between the controller and the PHY.  Examples are GMII, MII,
201	 RGMII, and SGMII.  For a full list, see include/linux/phy.h
203	 Now just make sure that phydev->supported and phydev->advertising have any
204	 values pruned from them which don't make sense for your controller (a 10/100
205	 controller may be connected to a gigabit capable PHY, so you would need to
206	 mask off SUPPORTED_1000baseT*).  See include/linux/ethtool.h for definitions
207	 for these bitfields. Note that you should not SET any bits, except the
208	 SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get
209	 put into an unsupported state.
211	 Lastly, once the controller is ready to handle network traffic, you call
212	 phy_start(phydev).  This tells the PAL that you are ready, and configures the
213	 PHY to connect to the network.  If you want to handle your own interrupts,
214	 just set phydev->irq to PHY_IGNORE_INTERRUPT before you call phy_start.
215	 Similarly, if you don't want to use interrupts, set phydev->irq to PHY_POLL.
217	 When you want to disconnect from the network (even if just briefly), you call
218	 phy_stop(phydev).
220	Pause frames / flow control
222	 The PHY does not participate directly in flow control/pause frames except by
223	 making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
224	 MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
225	 controller supports such a thing. Since flow control/pause frames generation
226	 involves the Ethernet MAC driver, it is recommended that this driver takes care
227	 of properly indicating advertisement and support for such features by setting
228	 the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
229	 either before or after phy_connect() and/or as a result of implementing the
230	 ethtool::set_pauseparam feature.
233	Keeping Close Tabs on the PAL
235	 It is possible that the PAL's built-in state machine needs a little help to
236	 keep your network device and the PHY properly in sync.  If so, you can
237	 register a helper function when connecting to the PHY, which will be called
238	 every second before the state machine reacts to any changes.  To do this, you
239	 need to manually call phy_attach() and phy_prepare_link(), and then call
240	 phy_start_machine() with the second argument set to point to your special
241	 handler.
243	 Currently there are no examples of how to use this functionality, and testing
244	 on it has been limited because the author does not have any drivers which use
245	 it (they all use option 1).  So Caveat Emptor.
247	Doing it all yourself
249	 There's a remote chance that the PAL's built-in state machine cannot track
250	 the complex interactions between the PHY and your network device.  If this is
251	 so, you can simply call phy_attach(), and not call phy_start_machine or
252	 phy_prepare_link().  This will mean that phydev->state is entirely yours to
253	 handle (phy_start and phy_stop toggle between some of the states, so you
254	 might need to avoid them).
256	 An effort has been made to make sure that useful functionality can be
257	 accessed without the state-machine running, and most of these functions are
258	 descended from functions which did not interact with a complex state-machine.
259	 However, again, no effort has been made so far to test running without the
260	 state machine, so tryer beware.
262	 Here is a brief rundown of the functions:
264	 int phy_read(struct phy_device *phydev, u16 regnum);
265	 int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
267	   Simple read/write primitives.  They invoke the bus's read/write function
268	   pointers.
270	 void phy_print_status(struct phy_device *phydev);
272	   A convenience function to print out the PHY status neatly.
274	 int phy_start_interrupts(struct phy_device *phydev);
275	 int phy_stop_interrupts(struct phy_device *phydev);
277	   Requests the IRQ for the PHY interrupts, then enables them for
278	   start, or disables then frees them for stop.
280	 struct phy_device * phy_attach(struct net_device *dev, const char *phy_id,
281			 phy_interface_t interface);
283	   Attaches a network device to a particular PHY, binding the PHY to a generic
284	   driver if none was found during bus initialization.
286	 int phy_start_aneg(struct phy_device *phydev);
288	   Using variables inside the phydev structure, either configures advertising
289	   and resets autonegotiation, or disables autonegotiation, and configures
290	   forced settings.
292	 static inline int phy_read_status(struct phy_device *phydev);
294	   Fills the phydev structure with up-to-date information about the current
295	   settings in the PHY.
297	 int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
299	   Ethtool convenience functions.
301	 int phy_mii_ioctl(struct phy_device *phydev,
302	                 struct mii_ioctl_data *mii_data, int cmd);
304	   The MII ioctl.  Note that this function will completely screw up the state
305	   machine if you write registers like BMCR, BMSR, ADVERTISE, etc.  Best to
306	   use this only to write registers which are not standard, and don't set off
307	   a renegotiation.
310	PHY Device Drivers
312	 With the PHY Abstraction Layer, adding support for new PHYs is
313	 quite easy.  In some cases, no work is required at all!  However,
314	 many PHYs require a little hand-holding to get up-and-running.
316	Generic PHY driver
318	 If the desired PHY doesn't have any errata, quirks, or special
319	 features you want to support, then it may be best to not add
320	 support, and let the PHY Abstraction Layer's Generic PHY Driver
321	 do all of the work.  
323	Writing a PHY driver
325	 If you do need to write a PHY driver, the first thing to do is
326	 make sure it can be matched with an appropriate PHY device.
327	 This is done during bus initialization by reading the device's
328	 UID (stored in registers 2 and 3), then comparing it to each
329	 driver's phy_id field by ANDing it with each driver's
330	 phy_id_mask field.  Also, it needs a name.  Here's an example:
332	   static struct phy_driver dm9161_driver = {
333	         .phy_id         = 0x0181b880,
334		 .name           = "Davicom DM9161E",
335		 .phy_id_mask    = 0x0ffffff0,
336		 ...
337	   }
339	 Next, you need to specify what features (speed, duplex, autoneg,
340	 etc) your PHY device and driver support.  Most PHYs support
341	 PHY_BASIC_FEATURES, but you can look in include/mii.h for other
342	 features.
344	 Each driver consists of a number of function pointers, documented
345	 in include/linux/phy.h under the phy_driver structure.
347	 Of these, only config_aneg and read_status are required to be
348	 assigned by the driver code.  The rest are optional.  Also, it is
349	 preferred to use the generic phy driver's versions of these two
350	 functions if at all possible: genphy_read_status and
351	 genphy_config_aneg.  If this is not possible, it is likely that
352	 you only need to perform some actions before and after invoking
353	 these functions, and so your functions will wrap the generic
354	 ones.
356	 Feel free to look at the Marvell, Cicada, and Davicom drivers in
357	 drivers/net/phy/ for examples (the lxt and qsemi drivers have
358	 not been tested as of this writing).
360	 The PHY's MMD register accesses are handled by the PAL framework
361	 by default, but can be overridden by a specific PHY driver if
362	 required. This could be the case if a PHY was released for
363	 manufacturing before the MMD PHY register definitions were
364	 standardized by the IEEE. Most modern PHYs will be able to use
365	 the generic PAL framework for accessing the PHY's MMD registers.
366	 An example of such usage is for Energy Efficient Ethernet support,
367	 implemented in the PAL. This support uses the PAL to access MMD
368	 registers for EEE query and configuration if the PHY supports
369	 the IEEE standard access mechanisms, or can use the PHY's specific
370	 access interfaces if overridden by the specific PHY driver. See
371	 the Micrel driver in drivers/net/phy/ for an example of how this
372	 can be implemented.
374	Board Fixups
376	 Sometimes the specific interaction between the platform and the PHY requires
377	 special handling.  For instance, to change where the PHY's clock input is,
378	 or to add a delay to account for latency issues in the data path.  In order
379	 to support such contingencies, the PHY Layer allows platform code to register
380	 fixups to be run when the PHY is brought up (or subsequently reset).
382	 When the PHY Layer brings up a PHY it checks to see if there are any fixups
383	 registered for it, matching based on UID (contained in the PHY device's phy_id
384	 field) and the bus identifier (contained in phydev->dev.bus_id).  Both must
385	 match, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided as
386	 wildcards for the bus ID and UID, respectively.
388	 When a match is found, the PHY layer will invoke the run function associated
389	 with the fixup.  This function is passed a pointer to the phy_device of
390	 interest.  It should therefore only operate on that PHY.
392	 The platform code can either register the fixup using phy_register_fixup():
394		int phy_register_fixup(const char *phy_id,
395			u32 phy_uid, u32 phy_uid_mask,
396			int (*run)(struct phy_device *));
398	 Or using one of the two stubs, phy_register_fixup_for_uid() and
399	 phy_register_fixup_for_id():
401	 int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
402			int (*run)(struct phy_device *));
403	 int phy_register_fixup_for_id(const char *phy_id,
404			int (*run)(struct phy_device *));
406	 The stubs set one of the two matching criteria, and set the other one to
407	 match anything.
409	 When phy_register_fixup() or *_for_uid()/*_for_id() is called at module,
410	 unregister fixup and free allocate memory are required.
412	 Call one of following function before unloading module.
414	 int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask);
415	 int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
416	 int phy_register_fixup_for_id(const char *phy_id);
418	Standards
420	 IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two:
421	 http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf
423	 RGMII v1.3:
424	 http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf
426	 RGMII v2.0:
427	 http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf
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