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Documentation / perf / qcom_l2_pmu.txt


Based on kernel version 4.16.1. Page generated on 2018-04-09 11:53 EST.

1	Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
2	=====================================================================
3	
4	This driver supports the L2 cache clusters found in Qualcomm Technologies
5	Centriq SoCs. There are multiple physical L2 cache clusters, each with their
6	own PMU. Each cluster has one or more CPUs associated with it.
7	
8	There is one logical L2 PMU exposed, which aggregates the results from
9	the physical PMUs.
10	
11	The driver provides a description of its available events and configuration
12	options in sysfs, see /sys/devices/l2cache_0.
13	
14	The "format" directory describes the format of the events.
15	
16	Events can be envisioned as a 2-dimensional array. Each column represents
17	a group of events. There are 8 groups. Only one entry from each
18	group can be in use at a time. If multiple events from the same group
19	are specified, the conflicting events cannot be counted at the same time.
20	
21	Events are specified as 0xCCG, where CC is 2 hex digits specifying
22	the code (array row) and G specifies the group (column) 0-7.
23	
24	In addition there is a cycle counter event specified by the value 0xFE
25	which is outside the above scheme.
26	
27	The driver provides a "cpumask" sysfs attribute which contains a mask
28	consisting of one CPU per cluster which will be used to handle all the PMU
29	events on that cluster.
30	
31	Examples for use with perf:
32	
33	  perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
34	
35	  perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
36	
37	The driver does not support sampling, therefore "perf record" will
38	not work. Per-task perf sessions are not supported.
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