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Documentation / video4linux / cx2341x / fw-upload.txt


Based on kernel version 4.7.2. Page generated on 2016-08-22 22:48 EST.

1	This document describes how to upload the cx2341x firmware to the card.
2	
3	How to find
4	===========
5	
6	See the web pages of the various projects that uses this chip for information
7	on how to obtain the firmware.
8	
9	The firmware stored in a Windows driver can be detected as follows:
10	
11	- Each firmware image is 256k bytes.
12	- The 1st 32-bit word of the Encoder image is 0x0000da7
13	- The 1st 32-bit word of the Decoder image is 0x00003a7
14	- The 2nd 32-bit word of both images is 0xaa55bb66
15	
16	How to load
17	===========
18	
19	- Issue the FWapi command to stop the encoder if it is running. Wait for the
20	  command to complete.
21	- Issue the FWapi command to stop the decoder if it is running. Wait for the
22	  command to complete.
23	- Issue the I2C command to the digitizer to stop emitting VSYNC events.
24	- Issue the FWapi command to halt the encoder's firmware.
25	- Sleep for 10ms.
26	- Issue the FWapi command to halt the decoder's firmware.
27	- Sleep for 10ms.
28	- Write 0x00000000 to register 0x2800 to stop the Video Display Module.
29	- Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
30	- Write 0x00000000 to register 0xA064 to ping? the APU.
31	- Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
32	- Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
33	- Write 0x00000001 to register 0x9050 to stop the SPU.
34	- Sleep for 10ms.
35	- Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
36	- Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
37	- Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
38	- Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
39	- Sleep for 512ms. (600ms is recommended)
40	- Transfer the encoder's firmware image to offset 0 in Encoder memory space.
41	- Transfer the decoder's firmware image to offset 0 in Decoder memory space.
42	- Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
43	  re-enable the SPU.
44	- Sleep for 1 second.
45	- Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
46	  to re-enable the VPU.
47	- Sleep for 1 second.
48	- Issue status API commands to both firmware images to verify.
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