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Documentation / x86 / entry_64.txt

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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:56 EST.

1	This file documents some of the kernel entries in
2	arch/x86/entry/entry_64.S.  A lot of this explanation is adapted from
3	an email from Ingo Molnar:
5	http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu>
7	The x86 architecture has quite a few different ways to jump into
8	kernel code.  Most of these entry points are registered in
9	arch/x86/kernel/traps.c and implemented in arch/x86/entry/entry_64.S
10	for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
11	arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
12	syscall entry points and thus provides for 32-bit processes the
13	ability to execute syscalls when running on 64-bit kernels.
15	The IDT vector assignments are listed in arch/x86/include/asm/irq_vectors.h.
17	Some of these entries are:
19	 - system_call: syscall instruction from 64-bit code.
21	 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
22	   either way.
24	 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
25	   code
27	 - interrupt: An array of entries.  Every IDT vector that doesn't
28	   explicitly point somewhere else gets set to the corresponding
29	   value in interrupts.  These point to a whole array of
30	   magically-generated functions that make their way to do_IRQ with
31	   the interrupt number as a parameter.
33	 - APIC interrupts: Various special-purpose interrupts for things
34	   like TLB shootdown.
36	 - Architecturally-defined exceptions like divide_error.
38	There are a few complexities here.  The different x86-64 entries
39	have different calling conventions.  The syscall and sysenter
40	instructions have their own peculiar calling conventions.  Some of
41	the IDT entries push an error code onto the stack; others don't.
42	IDT entries using the IST alternative stack mechanism need their own
43	magic to get the stack frames right.  (You can find some
44	documentation in the AMD APM, Volume 2, Chapter 8 and the Intel SDM,
45	Volume 3, Chapter 6.)
47	Dealing with the swapgs instruction is especially tricky.  Swapgs
48	toggles whether gs is the kernel gs or the user gs.  The swapgs
49	instruction is rather fragile: it must nest perfectly and only in
50	single depth, it should only be used if entering from user mode to
51	kernel mode and then when returning to user-space, and precisely
52	so. If we mess that up even slightly, we crash.
54	So when we have a secondary entry, already in kernel mode, we *must
55	not* use SWAPGS blindly - nor must we forget doing a SWAPGS when it's
56	not switched/swapped yet.
58	Now, there's a secondary complication: there's a cheap way to test
59	which mode the CPU is in and an expensive way.
61	The cheap way is to pick this info off the entry frame on the kernel
62	stack, from the CS of the ptregs area of the kernel stack:
64		xorl %ebx,%ebx
65		testl $3,CS+8(%rsp)
66		je error_kernelspace
69	The expensive (paranoid) way is to read back the MSR_GS_BASE value
70	(which is what SWAPGS modifies):
72		movl $1,%ebx
73		movl $MSR_GS_BASE,%ecx
74		rdmsr
75		testl %edx,%edx
76		js 1f   /* negative -> in kernel */
78		xorl %ebx,%ebx
79	1:	ret
81	If we are at an interrupt or user-trap/gate-alike boundary then we can
82	use the faster check: the stack will be a reliable indicator of
83	whether SWAPGS was already done: if we see that we are a secondary
84	entry interrupting kernel mode execution, then we know that the GS
85	base has already been switched. If it says that we interrupted
86	user-space execution then we must do the SWAPGS.
88	But if we are in an NMI/MCE/DEBUG/whatever super-atomic entry context,
89	which might have triggered right after a normal entry wrote CS to the
90	stack but before we executed SWAPGS, then the only safe way to check
91	for GS is the slower method: the RDMSR.
93	Therefore, super-atomic entries (except NMI, which is handled separately)
94	must use idtentry with paranoid=1 to handle gsbase correctly.  This
95	triggers three main behavior changes:
97	 - Interrupt entry will use the slower gsbase check.
98	 - Interrupt entry from user mode will switch off the IST stack.
99	 - Interrupt exit to kernel mode will not attempt to reschedule.
101	We try to only use IST entries and the paranoid entry code for vectors
102	that absolutely need the more expensive check for the GS base - and we
103	generate all 'normal' entry points with the regular (faster) paranoid=0
104	variant.
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