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Documentation / x86 / x86_64 / boot-options.txt

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Based on kernel version 4.16.1. Page generated on 2018-04-09 11:53 EST.

1	AMD64 specific boot options
3	There are many others (usually documented in driver documentation), but
4	only the AMD64 specific ones are listed here.
6	Machine check
8	   Please see Documentation/x86/x86_64/machinecheck for sysfs runtime tunables.
10	   mce=off
11			Disable machine check
12	   mce=no_cmci
13			Disable CMCI(Corrected Machine Check Interrupt) that
14			Intel processor supports.  Usually this disablement is
15			not recommended, but it might be handy if your hardware
16			is misbehaving.
17			Note that you'll get more problems without CMCI than with
18			due to the shared banks, i.e. you might get duplicated
19			error logs.
20	   mce=dont_log_ce
21			Don't make logs for corrected errors.  All events reported
22			as corrected are silently cleared by OS.
23			This option will be useful if you have no interest in any
24			of corrected errors.
25	   mce=ignore_ce
26			Disable features for corrected errors, e.g. polling timer
27			and CMCI.  All events reported as corrected are not cleared
28			by OS and remained in its error banks.
29			Usually this disablement is not recommended, however if
30			there is an agent checking/clearing corrected errors
31			(e.g. BIOS or hardware monitoring applications), conflicting
32			with OS's error handling, and you cannot deactivate the agent,
33			then this option will be a help.
34	   mce=no_lmce
35			Do not opt-in to Local MCE delivery. Use legacy method
36			to broadcast MCEs.
37	   mce=bootlog
38			Enable logging of machine checks left over from booting.
39			Disabled by default on AMD Fam10h and older because some BIOS
40			leave bogus ones.
41			If your BIOS doesn't do that it's a good idea to enable though
42			to make sure you log even machine check events that result
43			in a reboot. On Intel systems it is enabled by default.
44	   mce=nobootlog
45			Disable boot machine check logging.
46	   mce=tolerancelevel[,monarchtimeout] (number,number)
47			tolerance levels:
48			0: always panic on uncorrected errors, log corrected errors
49			1: panic or SIGBUS on uncorrected errors, log corrected errors
50			2: SIGBUS or log uncorrected errors, log corrected errors
51			3: never panic or SIGBUS, log all errors (for testing only)
52			Default is 1
53			Can be also set using sysfs which is preferable.
54			monarchtimeout:
55			Sets the time in us to wait for other CPUs on machine checks. 0
56			to disable.
57	   mce=bios_cmci_threshold
58			Don't overwrite the bios-set CMCI threshold. This boot option
59			prevents Linux from overwriting the CMCI threshold set by the
60			bios. Without this option, Linux always sets the CMCI
61			threshold to 1. Enabling this may make memory predictive failure
62			analysis less effective if the bios sets thresholds for memory
63			errors since we will not see details for all errors.
64	   mce=recovery
65			Force-enable recoverable machine check code paths
67	   nomce (for compatibility with i386): same as mce=off
69	   Everything else is in sysfs now.
71	APICs
73	   apic		 Use IO-APIC. Default
75	   noapic	 Don't use the IO-APIC.
77	   disableapic	 Don't use the local APIC
79	   nolapic	 Don't use the local APIC (alias for i386 compatibility)
81	   pirq=...	 See Documentation/x86/i386/IO-APIC.txt
83	   noapictimer	 Don't set up the APIC timer
85	   no_timer_check Don't check the IO-APIC timer. This can work around
86			 problems with incorrect timer initialization on some boards.
87	   apicpmtimer
88			 Do APIC timer calibration using the pmtimer. Implies
89			 apicmaintimer. Useful when your PIT timer is totally
90			 broken.
92	Timing
94	  notsc
95	  Don't use the CPU time stamp counter to read the wall time.
96	  This can be used to work around timing problems on multiprocessor systems
97	  with not properly synchronized CPUs.
99	  nohpet
100	  Don't use the HPET timer.
102	Idle loop
104	  idle=poll
105	  Don't do power saving in the idle loop using HLT, but poll for rescheduling
106	  event. This will make the CPUs eat a lot more power, but may be useful
107	  to get slightly better performance in multiprocessor benchmarks. It also
108	  makes some profiling using performance counters more accurate.
109	  Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
110	  CPUs) this option has no performance advantage over the normal idle loop.
111	  It may also interact badly with hyperthreading.
113	Rebooting
115	   reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] [, [w]arm | [c]old]
116	   bios	  Use the CPU reboot vector for warm reset
117	   warm   Don't set the cold reboot flag
118	   cold   Set the cold reboot flag
119	   triple Force a triple fault (init)
120	   kbd    Use the keyboard controller. cold reset (default)
121	   acpi   Use the ACPI RESET_REG in the FADT. If ACPI is not configured or the
122	          ACPI reset does not work, the reboot path attempts the reset using
123	          the keyboard controller.
124	   efi    Use efi reset_system runtime service. If EFI is not configured or the
125	          EFI reset does not work, the reboot path attempts the reset using
126	          the keyboard controller.
128	   Using warm reset will be much faster especially on big memory
129	   systems because the BIOS will not go through the memory check.
130	   Disadvantage is that not all hardware will be completely reinitialized
131	   on reboot so there may be boot problems on some systems.
133	   reboot=force
135	   Don't stop other CPUs on reboot. This can make reboot more reliable
136	   in some cases.
138	Non Executable Mappings
140	  noexec=on|off
142	  on      Enable(default)
143	  off     Disable
145	NUMA
147	  numa=off	Only set up a single NUMA node spanning all memory.
149	  numa=noacpi   Don't parse the SRAT table for NUMA setup
151	  numa=fake=<size>[MG]
152			If given as a memory unit, fills all system RAM with nodes of
153			size interleaved over physical nodes.
155	  numa=fake=<N>
156			If given as an integer, fills all system RAM with N fake nodes
157			interleaved over physical nodes.
159	ACPI
161	  acpi=off	Don't enable ACPI
162	  acpi=ht	Use ACPI boot table parsing, but don't enable ACPI
163			interpreter
164	  acpi=force	Force ACPI on (currently not needed)
166	  acpi=strict   Disable out of spec ACPI workarounds.
168	  acpi_sci={edge,level,high,low}  Set up ACPI SCI interrupt.
170	  acpi=noirq	Don't route interrupts
172	  acpi=nocmcff	Disable firmware first mode for corrected errors. This
173			disables parsing the HEST CMC error source to check if
174			firmware has set the FF flag. This may result in
175			duplicate corrected error reports.
177	PCI
179	  pci=off		Don't use PCI
180	  pci=conf1		Use conf1 access.
181	  pci=conf2		Use conf2 access.
182	  pci=rom		Assign ROMs.
183	  pci=assign-busses	Assign busses
184	  pci=irqmask=MASK	Set PCI interrupt mask to MASK
185	  pci=lastbus=NUMBER	Scan up to NUMBER busses, no matter what the mptable says.
186	  pci=noacpi		Don't use ACPI to set up PCI interrupt routing.
188	IOMMU (input/output memory management unit)
190	 Currently four x86-64 PCI-DMA mapping implementations exist:
192	   1. <arch/x86_64/kernel/pci-nommu.c>: use no hardware/software IOMMU at all
193	      (e.g. because you have < 3 GB memory).
194	      Kernel boot message: "PCI-DMA: Disabling IOMMU"
196	   2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
197	      Kernel boot message: "PCI-DMA: using GART IOMMU"
199	   3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
200	      e.g. if there is no hardware IOMMU in the system and it is need because
201	      you have >3GB memory or told the kernel to us it (iommu=soft))
202	      Kernel boot message: "PCI-DMA: Using software bounce buffering
203	      for IO (SWIOTLB)"
205	   4. <arch/x86_64/pci-calgary.c> : IBM Calgary hardware IOMMU. Used in IBM
206	      pSeries and xSeries servers. This hardware IOMMU supports DMA address
207	      mapping with memory protection, etc.
208	      Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
210	 iommu=[<size>][,noagp][,off][,force][,noforce][,leak[=<nr_of_leak_pages>]
211		[,memaper[=<order>]][,merge][,forcesac][,fullflush][,nomerge]
212		[,noaperture][,calgary]
214	  General iommu options:
215	    off                Don't initialize and use any kind of IOMMU.
216	    noforce            Don't force hardware IOMMU usage when it is not needed.
217	                       (default).
218	    force              Force the use of the hardware IOMMU even when it is
219	                       not actually needed (e.g. because < 3 GB memory).
220	    soft               Use software bounce buffering (SWIOTLB) (default for
221	                       Intel machines). This can be used to prevent the usage
222	                       of an available hardware IOMMU.
224	  iommu options only relevant to the AMD GART hardware IOMMU:
225	    <size>             Set the size of the remapping area in bytes.
226	    allowed            Overwrite iommu off workarounds for specific chipsets.
227	    fullflush          Flush IOMMU on each allocation (default).
228	    nofullflush        Don't use IOMMU fullflush.
229	    leak               Turn on simple iommu leak tracing (only when
230	                       CONFIG_IOMMU_LEAK is on). Default number of leak pages
231	                       is 20.
232	    memaper[=<order>]  Allocate an own aperture over RAM with size 32MB<<order.
233	                       (default: order=1, i.e. 64MB)
234	    merge              Do scatter-gather (SG) merging. Implies "force"
235	                       (experimental).
236	    nomerge            Don't do scatter-gather (SG) merging.
237	    noaperture         Ask the IOMMU not to touch the aperture for AGP.
238	    forcesac           Force single-address cycle (SAC) mode for masks <40bits
239	                       (experimental).
240	    noagp              Don't initialize the AGP driver and use full aperture.
241	    allowdac           Allow double-address cycle (DAC) mode, i.e. DMA >4GB.
242	                       DAC is used with 32-bit PCI to push a 64-bit address in
243	                       two cycles. When off all DMA over >4GB is forced through
244	                       an IOMMU or software bounce buffering.
245	    nodac              Forbid DAC mode, i.e. DMA >4GB.
246	    panic              Always panic when IOMMU overflows.
247	    calgary            Use the Calgary IOMMU if it is available
249	  iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
250	  implementation:
251	    swiotlb=<pages>[,force]
252	    <pages>            Prereserve that many 128K pages for the software IO
253	                       bounce buffering.
254	    force              Force all IO through the software TLB.
256	  Settings for the IBM Calgary hardware IOMMU currently found in IBM
257	  pSeries and xSeries machines:
259	    calgary=[64k,128k,256k,512k,1M,2M,4M,8M]
260	    calgary=[translate_empty_slots]
261	    calgary=[disable=<PCI bus number>]
262	    panic              Always panic when IOMMU overflows
264	    64k,...,8M - Set the size of each PCI slot's translation table
265	    when using the Calgary IOMMU. This is the size of the translation
266	    table itself in main memory. The smallest table, 64k, covers an IO
267	    space of 32MB; the largest, 8MB table, can cover an IO space of
268	    4GB. Normally the kernel will make the right choice by itself.
270	    translate_empty_slots - Enable translation even on slots that have
271	    no devices attached to them, in case a device will be hotplugged
272	    in the future.
274	    disable=<PCI bus number> - Disable translation on a given PHB. For
275	    example, the built-in graphics adapter resides on the first bridge
276	    (PCI bus number 0); if translation (isolation) is enabled on this
277	    bridge, X servers that access the hardware directly from user
278	    space might stop working. Use this option if you have devices that
279	    are accessed from userspace directly on some PCI host bridge.
281	Miscellaneous
283		nogbpages
284			Do not use GB pages for kernel direct mappings.
285		gbpages
286			Use GB pages for kernel direct mappings.
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