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Documentation / xtensa / mmu.txt




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Based on kernel version 4.9. Page generated on 2016-12-21 14:37 EST.

1	MMUv3 initialization sequence.
2	
3	The code in the initialize_mmu macro sets up MMUv3 memory mapping
4	identically to MMUv2 fixed memory mapping. Depending on
5	CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
6	located in addresses it was linked for (symbol undefined), or not
7	(symbol defined), so it needs to be position-independent.
8	
9	The code has the following assumptions:
10	  This code fragment is run only on an MMU v3.
11	  TLBs are in their reset state.
12	  ITLBCFG and DTLBCFG are zero (reset state).
13	  RASID is 0x04030201 (reset state).
14	  PS.RING is zero (reset state).
15	  LITBASE is zero (reset state, PC-relative literals); required to be PIC.
16	
17	TLB setup proceeds along the following steps.
18	
19	  Legend:
20	    VA = virtual address (two upper nibbles of it);
21	    PA = physical address (two upper nibbles of it);
22	    pc = physical range that contains this code;
23	
24	After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
25	or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
26	0x40000000 or above. That address corresponds to next instruction to execute
27	in this code. After step 4, we jump to intended (linked) address of this code.
28	The scheme below assumes that the kernel is loaded below 0x40000000.
29	
30	        Step0  Step1  Step2  Step3          Step4  Step5
31	        =====  =====  =====  =====          =====  =====
32	   VA      PA     PA     PA     PA     VA      PA     PA
33	 ------    --     --     --     --   ------    --     --
34	 E0..FF -> E0  -> E0  -> E0          F0..FF -> F0  -> F0
35	 C0..DF -> C0  -> C0  -> C0          E0..EF -> F0  -> F0
36	 A0..BF -> A0  -> A0  -> A0          D8..DF -> 00  -> 00
37	 80..9F -> 80  -> 80  -> 80          D0..D7 -> 00  -> 00
38	 60..7F -> 60  -> 60  -> 60
39	 40..5F -> 40         -> pc  -> pc   40..5F -> pc
40	 20..3F -> 20  -> 20  -> 20
41	 00..1F -> 00  -> 00  -> 00
42	
43	The default location of IO peripherals is above 0xf0000000. This may be changed
44	using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, §6.5
45	for details on the syntax and semantic of simple-bus nodes. The following
46	limitations apply:
47	
48	1. Only top level simple-bus nodes are considered
49	
50	2. Only one (first) simple-bus node is considered
51	
52	3. Empty "ranges" properties are not supported
53	
54	4. Only the first triplet in the "ranges" property is considered
55	
56	5. The parent-bus-address value is rounded down to the nearest 256MB boundary
57	
58	6. The IO area covers the entire 256MB segment of parent-bus-address; the
59	   "ranges" triplet length field is ignored
60	
61	
62	MMUv3 address space layouts.
63	============================
64	
65	Default MMUv2-compatible layout.
66	
67	                      Symbol                   VADDR       Size
68	+------------------+
69	| Userspace        |                           0x00000000  TASK_SIZE
70	+------------------+                           0x40000000
71	+------------------+
72	| Page table       |                           0x80000000
73	+------------------+                           0x80400000
74	+------------------+
75	| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
76	|                  |                                       DCACHE_N_COLORS *
77	|                  |                                       PAGE_SIZE
78	|                  |                                       (4MB * DCACHE_N_COLORS)
79	+------------------+
80	| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
81	|                  |                                       NR_CPUS *
82	|                  |                                       DCACHE_N_COLORS *
83	|                  |                                       PAGE_SIZE
84	+------------------+  FIXADDR_TOP              0xbffff000
85	+------------------+
86	| VMALLOC area     |  VMALLOC_START            0xc0000000  128MB - 64KB
87	+------------------+  VMALLOC_END
88	| Cache aliasing   |  TLBTEMP_BASE_1           0xc7ff0000  DCACHE_WAY_SIZE
89	| remap area 1     |
90	+------------------+
91	| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
92	| remap area 2     |
93	+------------------+
94	+------------------+
95	| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xd0000000  128MB
96	+------------------+
97	| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xd8000000  128MB
98	+------------------+
99	| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
100	+------------------+
101	| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
102	+------------------+
103	
104	
105	256MB cached + 256MB uncached layout.
106	
107	                      Symbol                   VADDR       Size
108	+------------------+
109	| Userspace        |                           0x00000000  TASK_SIZE
110	+------------------+                           0x40000000
111	+------------------+
112	| Page table       |                           0x80000000
113	+------------------+                           0x80400000
114	+------------------+
115	| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
116	|                  |                                       DCACHE_N_COLORS *
117	|                  |                                       PAGE_SIZE
118	|                  |                                       (4MB * DCACHE_N_COLORS)
119	+------------------+
120	| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
121	|                  |                                       NR_CPUS *
122	|                  |                                       DCACHE_N_COLORS *
123	|                  |                                       PAGE_SIZE
124	+------------------+  FIXADDR_TOP              0x9ffff000
125	+------------------+
126	| VMALLOC area     |  VMALLOC_START            0xa0000000  128MB - 64KB
127	+------------------+  VMALLOC_END
128	| Cache aliasing   |  TLBTEMP_BASE_1           0xa7ff0000  DCACHE_WAY_SIZE
129	| remap area 1     |
130	+------------------+
131	| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
132	| remap area 2     |
133	+------------------+
134	+------------------+
135	| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xb0000000  256MB
136	+------------------+
137	| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  256MB
138	+------------------+
139	+------------------+
140	| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
141	+------------------+
142	| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
143	+------------------+
144	
145	
146	512MB cached + 512MB uncached layout.
147	
148	                      Symbol                   VADDR       Size
149	+------------------+
150	| Userspace        |                           0x00000000  TASK_SIZE
151	+------------------+                           0x40000000
152	+------------------+
153	| Page table       |                           0x80000000
154	+------------------+                           0x80400000
155	+------------------+
156	| KMAP area        |  PKMAP_BASE                           PTRS_PER_PTE *
157	|                  |                                       DCACHE_N_COLORS *
158	|                  |                                       PAGE_SIZE
159	|                  |                                       (4MB * DCACHE_N_COLORS)
160	+------------------+
161	| Atomic KMAP area |  FIXADDR_START                        KM_TYPE_NR *
162	|                  |                                       NR_CPUS *
163	|                  |                                       DCACHE_N_COLORS *
164	|                  |                                       PAGE_SIZE
165	+------------------+  FIXADDR_TOP              0x8ffff000
166	+------------------+
167	| VMALLOC area     |  VMALLOC_START            0x90000000  128MB - 64KB
168	+------------------+  VMALLOC_END
169	| Cache aliasing   |  TLBTEMP_BASE_1           0x97ff0000  DCACHE_WAY_SIZE
170	| remap area 1     |
171	+------------------+
172	| Cache aliasing   |  TLBTEMP_BASE_2                       DCACHE_WAY_SIZE
173	| remap area 2     |
174	+------------------+
175	+------------------+
176	| Cached KSEG      |  XCHAL_KSEG_CACHED_VADDR  0xa0000000  512MB
177	+------------------+
178	| Uncached KSEG    |  XCHAL_KSEG_BYPASS_VADDR  0xc0000000  512MB
179	+------------------+
180	| Cached KIO       |  XCHAL_KIO_CACHED_VADDR   0xe0000000  256MB
181	+------------------+
182	| Uncached KIO     |  XCHAL_KIO_BYPASS_VADDR   0xf0000000  256MB
183	+------------------+
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