Documentation / devicetree / bindings / arm / coresight.txt


Based on kernel version 5.19.17. Page generated on 2023-08-28 22:14 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402
* CoreSight Components:

CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink. Each CoreSight component device should use these properties to describe
its hardware characteristcs.

* Required properties for all components *except* non-configurable replicators
  and non-configurable funnels:

	* compatible: These have to be supplemented with "arm,primecell" as
	  drivers are using the AMBA bus interface.  Possible values include:
		- Embedded Trace Buffer (version 1.0):
			"arm,coresight-etb10", "arm,primecell";

		- Trace Port Interface Unit:
			"arm,coresight-tpiu", "arm,primecell";

		- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
		  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
		  configuration.  The configuration mode (ETB, ETF, ETR) is
		  discovered at boot time when the device is probed.
			"arm,coresight-tmc", "arm,primecell";

		- Trace Programmable Funnel:
			"arm,coresight-dynamic-funnel", "arm,primecell";
			"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
				backward compatibility and will be removed)

		- Embedded Trace Macrocell (version 3.x) and
					Program Flow Trace Macrocell:
			"arm,coresight-etm3x", "arm,primecell";

		- Embedded Trace Macrocell (version 4.x), with memory mapped access.
			"arm,coresight-etm4x", "arm,primecell";

		- Embedded Trace Macrocell (version 4.x), with system register access only.
			"arm,coresight-etm4x-sysreg";

		- Coresight programmable Replicator :
			"arm,coresight-dynamic-replicator", "arm,primecell";

		- System Trace Macrocell:
			"arm,coresight-stm", "arm,primecell"; [1]
		- Coresight Address Translation Unit (CATU)
			"arm,coresight-catu", "arm,primecell";

		- Coresight Cross Trigger Interface (CTI):
			"arm,coresight-cti", "arm,primecell";
			See coresight-cti.yaml for full CTI definitions.

	* reg: physical base address and length of the register
	  set(s) of the component.

	* clocks: the clocks associated to this component.

	* clock-names: the name of the clocks referenced by the code.
	  Since we are using the AMBA framework, the name of the clock
	  providing the interconnect should be "apb_pclk", and some
	  coresight blocks also have an additional clock "atclk", which
	  clocks the core of that coresight component. The latter clock
	  is optional.

	* port or ports: see "Graph bindings for Coresight" below.

* Additional required property for Embedded Trace Macrocell (version 3.x and
  version 4.x):
	* cpu: the cpu phandle this ETM/PTM is affined to. Do not
	  assume it to default to CPU0 if omitted.

* Additional required properties for System Trace Macrocells (STM):
	* reg: along with the physical base address and length of the register
	  set as described above, another entry is required to describe the
	  mapping of the extended stimulus port area.

	* reg-names: the only acceptable values are "stm-base" and
	  "stm-stimulus-base", each corresponding to the areas defined in "reg".

* Required properties for Coresight Cross Trigger Interface (CTI)
	See coresight-cti.yaml for full CTI definitions.

* Required properties for devices that don't show up on the AMBA bus, such as
  non-configurable replicators and non-configurable funnels:

	* compatible: Currently supported value is (note the absence of the
	  AMBA markee):
		- Coresight Non-configurable Replicator:
			"arm,coresight-static-replicator";
			"arm,coresight-replicator"; (OBSOLETE. For backward
				compatibility and will be removed)

		- Coresight Non-configurable Funnel:
			"arm,coresight-static-funnel";

	* port or ports: see "Graph bindings for Coresight" below.

* Optional properties for all components:

	* arm,coresight-loses-context-with-cpu : boolean. Indicates that the
	  hardware will lose register context on CPU power down (e.g. CPUIdle).
	  An example of where this may be needed are systems which contain a
	  coresight component and CPU in the same power domain. When the CPU
	  powers down the coresight component also powers down and loses its
	  context. This property is currently only used for the ETM 4.x driver.

* Optional properties for ETM/PTMs:

	* arm,cp14: must be present if the system accesses ETM/PTM management
	  registers via co-processor 14.

	* qcom,skip-power-up: boolean. Indicates that an implementation can
	  skip powering up the trace unit. TRCPDCR.PU does not have to be set
	  on Qualcomm Technologies Inc. systems since ETMs are in the same power
	  domain as their CPU cores. This property is required to identify such
	  systems with hardware errata where the CPU watchdog counter is stopped
	  when TRCPDCR.PU is set.

* Optional property for TMC:

	* arm,buffer-size: size of contiguous buffer space for TMC ETR
	  (embedded trace router). This property is obsolete. The buffer size
	  can be configured dynamically via buffer_size property in sysfs.

	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
	  use the SG mode on this system.

	* arm,max-burst-size: The maximum burst size initiated by TMC on the
	  AXI master interface. The burst size can be in the range [0..15],
	  the setting supports one data transfer per burst up to a maximum of
	  16 data transfers per burst.

* Optional property for CATU :
	* interrupts : Exactly one SPI may be listed for reporting the address
	  error

* Optional property for configurable replicators:

	* qcom,replicator-loses-context: boolean. Indicates that the replicator
	  will lose register context when AMBA clock is removed which is observed
	  in some replicator designs.

Graph bindings for Coresight
-------------------------------

Coresight components are interconnected to create a data path for the flow of
trace data generated from the "sources" to their collection points "sink".
Each coresight component must describe the "input" and "output" connections.
The connections must be described via generic DT graph bindings as described
by the "bindings/graph.txt", where each "port" along with an "endpoint"
component represents a hardware port and the connection.

 * All output ports must be listed inside a child node named "out-ports"
 * All input ports must be listed inside a child node named "in-ports".
 * Port address must match the hardware port number.

Example:

1. Sinks
	etb@20010000 {
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		in-ports {
			port {
				etb_in_port: endpoint@0 {
					remote-endpoint = <&replicator_out_port0>;
				};
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		in-ports {
			port {
				tpiu_in_port: endpoint@0 {
					remote-endpoint = <&replicator_out_port1>;
				};
			};
		};
	};

	etr@20070000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20070000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		in-ports {
			port {
				etr_in_port: endpoint {
					remote-endpoint = <&replicator2_out_port0>;
				};
			};
		};

		out-ports {
			port {
				etr_out_port: endpoint {
					remote-endpoint = <&catu_in_port>;
				};
			};
		};
	};

2. Links
	replicator {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-static-replicator";

		out-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&etb_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};
		};

		in-ports {
			port {
				replicator_in_port0: endpoint {
					remote-endpoint = <&funnel_out_port0>;
				};
			};
		};
	};

	funnel {
		/*
		 * non-configurable funnel don't show up on the AMBA
		 * bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-static-funnel";
		clocks = <&crg_ctrl HI3660_PCLK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				combo_funnel_out: endpoint {
					remote-endpoint = <&top_funnel_in>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				combo_funnel_in0: endpoint {
					remote-endpoint = <&cluster0_etf_out>;
				};
			};

			port@1 {
				reg = <1>;
				combo_funnel_in1: endpoint {
					remote-endpoint = <&cluster1_etf_out>;
				};
			};
		};
	};

	funnel@20040000 {
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				funnel_out_port0: endpoint {
					remote-endpoint =
							<&replicator_in_port0>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in_port0: endpoint {
					remote-endpoint = <&ptm0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_in_port1: endpoint {
					remote-endpoint = <&ptm1_out_port>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_in_port2: endpoint {
					remote-endpoint = <&etm0_out_port>;
				};
			};

		};
	};

3. Sources
	ptm@2201c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201c000 0 0x1000>;

		cpu = <&cpu0>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				ptm0_out_port: endpoint {
					remote-endpoint = <&funnel_in_port0>;
				};
			};
		};
	};

	ptm@2201d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201d000 0 0x1000>;

		cpu = <&cpu1>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				ptm1_out_port: endpoint {
					remote-endpoint = <&funnel_in_port1>;
				};
			};
		};
	};

4. STM
	stm@20100000 {
		compatible = "arm,coresight-stm", "arm,primecell";
		reg = <0 0x20100000 0 0x1000>,
		      <0 0x28000000 0 0x180000>;
		reg-names = "stm-base", "stm-stimulus-base";

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				stm_out_port: endpoint {
					remote-endpoint = <&main_funnel_in_port2>;
				};
			};
		};
	};

5. CATU

	catu@207e0000 {
		compatible = "arm,coresight-catu", "arm,primecell";
		reg = <0 0x207e0000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		in-ports {
			port {
				catu_in_port: endpoint {
					remote-endpoint = <&etr_out_port>;
				};
			};
		};
	};

[1]. There is currently two version of STM: STM32 and STM500.  Both
have the same HW interface and as such don't need an explicit binding name.