Documentation / devicetree / bindings / cpufreq / qcom-cpufreq-nvmem.yaml


Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. NVMEM CPUFreq

maintainers:
  - Ilia Lin <ilia.lin@kernel.org>

description: |
  In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
  voltage is dynamically configured by Core Power Reduction (CPR) depending on
  current CPU frequency and efuse values.
  CPR provides a power domain with multiple levels that are selected depending
  on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
  according to the required OPPs defined in the CPU OPP tables.
 
  For old implementation efuses are parsed to select the correct opp table and
  voltage and CPR is not supported/used.

select:
  properties:
    compatible:
      contains:
        enum:
          - qcom,apq8064
          - qcom,apq8096
          - qcom,ipq5332
          - qcom,ipq6018
          - qcom,ipq8064
          - qcom,ipq8074
          - qcom,ipq9574
          - qcom,msm8909
          - qcom,msm8939
          - qcom,msm8960
          - qcom,msm8974
          - qcom,msm8996
          - qcom,qcs404
  required:
    - compatible

patternProperties:
  '^opp-table(-[a-z0-9]+)?$':
    allOf:
      - if:
          properties:
            compatible:
              enum:
                - operating-points-v2-krait-cpu
                - operating-points-v2-kryo-cpu
        then:
          $ref: /schemas/opp/opp-v2-kryo-cpu.yaml#

      - if:
          properties:
            compatible:
              const: operating-points-v2-qcom-level
        then:
          $ref: /schemas/opp/opp-v2-qcom-level.yaml#

    unevaluatedProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,qcs404

    then:
      properties:
        cpus:
          type: object

          patternProperties:
            '^cpu@[0-9a-f]+$':
              type: object

              properties:
                power-domains:
                  maxItems: 1

                power-domain-names:
                  items:
                    - const: cpr

              required:
                - power-domains
                - power-domain-names

      patternProperties:
        '^opp-table(-[a-z0-9]+)?$':
          if:
            properties:
              compatible:
                const: operating-points-v2-kryo-cpu
          then:
            patternProperties:
              '^opp-?[0-9]+$':
                required:
                  - required-opps

additionalProperties: true

examples:
  - |
    / {
        model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
        compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
        #address-cells = <2>;
        #size-cells = <2>;
 
        cpus {
            #address-cells = <1>;
            #size-cells = <0>;
 
            CPU0: cpu@100 {
                device_type = "cpu";
                compatible = "arm,cortex-a53";
                reg = <0x100>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                next-level-cache = <&L2_0>;
                #cooling-cells = <2>;
                clocks = <&apcs_glb>;
                operating-points-v2 = <&cpu_opp_table>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
            };
 
            CPU1: cpu@101 {
                device_type = "cpu";
                compatible = "arm,cortex-a53";
                reg = <0x101>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                next-level-cache = <&L2_0>;
                #cooling-cells = <2>;
                clocks = <&apcs_glb>;
                operating-points-v2 = <&cpu_opp_table>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
            };
 
            CPU2: cpu@102 {
                device_type = "cpu";
                compatible = "arm,cortex-a53";
                reg = <0x102>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                next-level-cache = <&L2_0>;
                #cooling-cells = <2>;
                clocks = <&apcs_glb>;
                operating-points-v2 = <&cpu_opp_table>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
            };
 
            CPU3: cpu@103 {
                device_type = "cpu";
                compatible = "arm,cortex-a53";
                reg = <0x103>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                next-level-cache = <&L2_0>;
                #cooling-cells = <2>;
                clocks = <&apcs_glb>;
                operating-points-v2 = <&cpu_opp_table>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
            };
        };
 
        cpu_opp_table: opp-table-cpu {
            compatible = "operating-points-v2-kryo-cpu";
            opp-shared;
 
            opp-1094400000 {
                opp-hz = /bits/ 64 <1094400000>;
                required-opps = <&cpr_opp1>;
            };
            opp-1248000000 {
                opp-hz = /bits/ 64 <1248000000>;
                required-opps = <&cpr_opp2>;
            };
            opp-1401600000 {
                opp-hz = /bits/ 64 <1401600000>;
                required-opps = <&cpr_opp3>;
            };
        };
 
        cpr_opp_table: opp-table-cpr {
            compatible = "operating-points-v2-qcom-level";
 
            cpr_opp1: opp1 {
                opp-level = <1>;
                qcom,opp-fuse-level = <1>;
            };
            cpr_opp2: opp2 {
                opp-level = <2>;
                qcom,opp-fuse-level = <2>;
            };
            cpr_opp3: opp3 {
                opp-level = <3>;
                qcom,opp-fuse-level = <3>;
            };
        };
    };