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Documentation / devicetree / bindings / gpio / gpio-stp-xway.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	Lantiq SoC Serial To Parallel (STP) GPIO controller
2	
3	The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
4	peripheral controller used to drive external shift register cascades. At most
5	3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
6	to drive the 2 LSBs of the cascade automatically.
7	
8	
9	Required properties:
10	- compatible : Should be "lantiq,gpio-stp-xway"
11	- reg : Address and length of the register set for the device
12	- #gpio-cells : Should be two.  The first cell is the pin number and
13	  the second cell is used to specify optional parameters (currently
14	  unused).
15	- gpio-controller : Marks the device node as a gpio controller.
16	
17	Optional properties:
18	- lantiq,shadow : The default value that we shall assume as already set on the
19	  shift register cascade.
20	- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
21	  in the shift register cascade.
22	- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
23	  property can enable this feature.
24	- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
25	- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
26	- lantiq,rising : use rising instead of falling edge for the shift register
27	
28	Example:
29	
30	gpio1: stp@E100BB0 {
31		compatible = "lantiq,gpio-stp-xway";
32		reg = <0xE100BB0 0x40>;
33		#gpio-cells = <2>;
34		gpio-controller;
35	
36		lantiq,shadow = <0xffff>;
37		lantiq,groups = <0x7>;
38		lantiq,dsl = <0x3>;
39		lantiq,phy1 = <0x7>;
40		lantiq,phy2 = <0x7>;
41		/* lantiq,rising; */
42	};
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