Documentation / devicetree / bindings / memory-controllers / ddr / jedec,lpddr2-timings.yaml


Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR2 SDRAM AC timing parameters for a given speed-bin

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: jedec,lpddr2-timings

  max-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Maximum DDR clock frequency for the speed-bin, in Hz.

  min-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Minimum DDR clock frequency for the speed-bin, in Hz.

  tCKESR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in pico seconds.

  tDQSCK-max:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DQS output data access time from CK_t/CK_c in pico seconds.

  tDQSCK-max-derated:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
      seconds.

  tFAW:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Four-bank activate window in pico seconds.

  tRAS-max-ns:
    description: |
      Row active time in nano seconds.

  tRAS-min:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row active time in pico seconds.

  tRCD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RAS-to-CAS delay in pico seconds.

  tRPab:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row precharge time (all banks) in pico seconds.

  tRRD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Active bank A to active bank B in pico seconds.

  tRTP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal READ to PRECHARGE command delay in pico seconds.

  tWR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      WRITE recovery time in pico seconds.

  tWTR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal WRITE-to-READ command delay in pico seconds.

  tXP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Exit power-down to next valid command delay in pico seconds.

  tZQCL:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Long calibration time in pico seconds.

  tZQCS:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Short calibration time in pico seconds.

  tZQinit:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Initialization calibration time in pico seconds.

required:
  - compatible
  - min-freq
  - max-freq

additionalProperties: false

examples:
  - |
    timings {
        compatible = "jedec,lpddr2-timings";
        min-freq = <10000000>;
        max-freq = <400000000>;
        tCKESR = <15000>;
        tDQSCK-max = <5500>;
        tFAW = <50000>;
        tRAS-max-ns = <70000>;
        tRAS-min = <42000>;
        tRPab = <21000>;
        tRCD = <18000>;
        tRRD = <10000>;
        tRTP = <7500>;
        tWR = <15000>;
        tWTR = <7500>;
        tXP = <7500>;
        tZQCL = <360000>;
        tZQCS = <90000>;
        tZQinit = <1000000>;
    };