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Based on kernel version 3.19. Page generated on 2015-02-13 21:18 EST.

1	Marvell Distributed Switch Architecture Device Tree Bindings
2	------------------------------------------------------------
3	
4	Required properties:
5	- compatible		: Should be "marvell,dsa"
6	- #address-cells	: Must be 2, first cell is the address on the MDIO bus
7				  and second cell is the address in the switch tree.
8				  Second cell is used only when cascading/chaining.
9	- #size-cells		: Must be 0
10	- dsa,ethernet		: Should be a phandle to a valid Ethernet device node
11	- dsa,mii-bus		: Should be a phandle to a valid MDIO bus device node
12	
13	Optional properties:
14	- interrupts		: property with a value describing the switch
15				  interrupt number (not supported by the driver)
16	
17	A DSA node can contain multiple switch chips which are therefore child nodes of
18	the parent DSA node. The maximum number of allowed child nodes is 4
19	(DSA_MAX_SWITCHES).
20	Each of these switch child nodes should have the following required properties:
21	
22	- reg			: Describes the switch address on the MII bus
23	- #address-cells	: Must be 1
24	- #size-cells		: Must be 0
25	
26	A switch child node has the following optional property:
27	
28	- eeprom-length		: Set to the length of an EEPROM connected to the
29				  switch. Must be set if the switch can not detect
30				  the presence and/or size of a connected EEPROM,
31				  otherwise optional.
32	
33	A switch may have multiple "port" children nodes
34	
35	Each port children node must have the following mandatory properties:
36	- reg			: Describes the port address in the switch
37	- label			: Describes the label associated with this port, special
38				  labels are "cpu" to indicate a CPU port and "dsa" to
39				  indicate an uplink/downlink port.
40	
41	Note that a port labelled "dsa" will imply checking for the uplink phandle
42	described below.
43	
44	Optionnal property:
45	- link			: Should be a phandle to another switch's DSA port.
46				  This property is only used when switches are being
47				  chained/cascaded together.
48	
49	- phy-handle		: Phandle to a PHY on an external MDIO bus, not the
50				  switch internal one. See
51				  Documentation/devicetree/bindings/net/ethernet.txt
52				  for details.
53	
54	- phy-mode		: String representing the connection to the designated
55				  PHY node specified by the 'phy-handle' property. See
56				  Documentation/devicetree/bindings/net/ethernet.txt
57				  for details.
58	
59	Optional subnodes:
60	- fixed-link		: Fixed-link subnode describing a link to a non-MDIO
61				  managed entity. See
62				  Documentation/devicetree/bindings/net/fixed-link.txt
63				  for details.
64	
65	Example:
66	
67		dsa@0 {
68			compatible = "marvell,dsa";
69			#address-cells = <2>;
70			#size-cells = <0>;
71	
72			interrupts = <10>;
73			dsa,ethernet = <&ethernet0>;
74			dsa,mii-bus = <&mii_bus0>;
75	
76			switch@0 {
77				#address-cells = <1>;
78				#size-cells = <0>;
79				reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
80	
81				port@0 {
82					reg = <0>;
83					label = "lan1";
84					phy-handle = <&phy0>;
85				};
86	
87				port@1 {
88					reg = <1>;
89					label = "lan2";
90				};
91	
92				port@5 {
93					reg = <5>;
94					label = "cpu";
95				};
96	
97				switch0uplink: port@6 {
98					reg = <6>;
99					label = "dsa";
100					link = <&switch1uplink>;
101				};
102			};
103	
104			switch@1 {
105				#address-cells = <1>;
106				#size-cells = <0>;
107				reg = <17 1>;	/* MDIO address 17, switch 1 in tree */
108	
109				switch1uplink: port@0 {
110					reg = <0>;
111					label = "dsa";
112					link = <&switch0uplink>;
113				};
114			};
115		};
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