Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/dsa/realtek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek switches for unmanaged switches allOf: - $ref: dsa.yaml#/$defs/ethernet-ports maintainers: - Linus Walleij <linus.walleij@linaro.org> description: Realtek advertises these chips as fast/gigabit switches or unmanaged switches. They can be controlled using different interfaces, like SMI, MDIO or SPI. The SMI "Simple Management Interface" is a two-wire protocol using bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does not use the MDIO protocol. This binding defines how to specify the SMI-based Realtek devices. The realtek-smi driver is a platform driver and it must be inserted inside a platform node. The MDIO-connected switches use MDIO protocol to access their registers. The realtek-mdio driver is an MDIO driver and it must be inserted inside an MDIO node. The compatible string is only used to identify which (silicon) family the switch belongs to. Roughly speaking, a family is any set of Realtek switches whose chip identification register(s) have a common location and semantics. The different models in a given family can be automatically disambiguated by parsing the chip identification register(s) according to the given family, avoiding the need for a unique compatible string for each model. properties: compatible: enum: - realtek,rtl8365mb - realtek,rtl8366rb description: | realtek,rtl8365mb: Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S, RTL8367SB, RTL8370MB, RTL8310SR realtek,rtl8366rb: Use with models RTL8366RB, RTL8366S mdc-gpios: description: GPIO line for the MDC clock line. maxItems: 1 mdio-gpios: description: GPIO line for the MDIO data line. maxItems: 1 reset-gpios: description: GPIO to be used to reset the whole device maxItems: 1 realtek,disable-leds: type: boolean description: | if the LED drivers are not used in the hardware design, this will disable them so they are not turned on and wasting power. interrupt-controller: type: object additionalProperties: false description: | This defines an interrupt controller with an IRQ line (typically a GPIO) that will demultiplex and handle the interrupt from the single interrupt line coming out of one of the Realtek switch chips. It most importantly provides link up/down interrupts to the PHY blocks inside the ASIC. properties: interrupt-controller: true interrupts: maxItems: 1 description: A single IRQ line from the switch, either active LOW or HIGH '#address-cells': const: 0 '#interrupt-cells': const: 1 required: - interrupt-controller - '#address-cells' - '#interrupt-cells' mdio: $ref: /schemas/net/mdio.yaml# unevaluatedProperties: false properties: compatible: const: realtek,smi-mdio if: required: - reg then: $ref: /schemas/spi/spi-peripheral-props.yaml# not: required: - mdc-gpios - mdio-gpios - mdio properties: mdc-gpios: false mdio-gpios: false mdio: false else: required: - mdc-gpios - mdio-gpios - mdio - reset-gpios required: - compatible # - mdc-gpios # - mdio-gpios # - reset-gpios # - mdio unevaluatedProperties: false examples: - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> platform { switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; switch_intc1: interrupt-controller { /* GPIO 15 provides the interrupt */ interrupt-parent = <&gpio0>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan0"; phy-handle = <&phy0>; }; port@1 { reg = <1>; label = "lan1"; phy-handle = <&phy1>; }; port@2 { reg = <2>; label = "lan2"; phy-handle = <&phy2>; }; port@3 { reg = <3>; label = "lan3"; phy-handle = <&phy3>; }; port@4 { reg = <4>; label = "wan"; phy-handle = <&phy4>; }; port@5 { reg = <5>; ethernet = <&gmac0>; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; }; }; }; mdio { compatible = "realtek,smi-mdio"; #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch_intc1>; interrupts = <0>; }; phy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch_intc1>; interrupts = <1>; }; phy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch_intc1>; interrupts = <2>; }; phy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch_intc1>; interrupts = <3>; }; phy4: ethernet-phy@4 { reg = <4>; interrupt-parent = <&switch_intc1>; interrupts = <12>; }; }; }; }; - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> platform { switch { compatible = "realtek,rtl8365mb"; mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; switch_intc2: interrupt-controller { interrupt-parent = <&gpio5>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "swp0"; phy-handle = <ðphy0>; }; port@1 { reg = <1>; label = "swp1"; phy-handle = <ðphy1>; }; port@2 { reg = <2>; label = "swp2"; phy-handle = <ðphy2>; }; port@3 { reg = <3>; label = "swp3"; phy-handle = <ðphy3>; }; port@6 { reg = <6>; ethernet = <&fec1>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; rx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; mdio { compatible = "realtek,smi-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch_intc2>; interrupts = <0>; }; ethphy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch_intc2>; interrupts = <1>; }; ethphy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch_intc2>; interrupts = <2>; }; ethphy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch_intc2>; interrupts = <3>; }; }; }; }; - | #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> mdio { #address-cells = <1>; #size-cells = <0>; switch@29 { compatible = "realtek,rtl8365mb"; reg = <29>; reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; switch_intc3: interrupt-controller { interrupt-parent = <&gpio0>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan4"; }; port@1 { reg = <1>; label = "lan3"; }; port@2 { reg = <2>; label = "lan2"; }; port@3 { reg = <3>; label = "lan1"; }; port@4 { reg = <4>; label = "wan"; }; port@7 { reg = <7>; ethernet = <ðernet>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; rx-internal-delay-ps = <0>; fixed-link { speed = <1000>; full-duplex; }; }; }; }; }; |