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Documentation / devicetree / bindings / pinctrl / atmel,at91-pinctrl.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:01 EST.

1	* Atmel AT91 Pinmux Controller
2	
3	The AT91 Pinmux Controller, enables the IC
4	to share one PAD to several functional blocks. The sharing is done by
5	multiplexing the PAD input/output signals. For each PAD there are up to
6	8 muxing options (called periph modes). Since different modules require
7	different PAD settings (like pull up, keeper, etc) the contoller controls
8	also the PAD settings parameters.
9	
10	Please refer to pinctrl-bindings.txt in this directory for details of the
11	common pinctrl bindings used by client devices, including the meaning of the
12	phrase "pin configuration node".
13	
14	Atmel AT91 pin configuration node is a node of a group of pins which can be
15	used for a specific device or function. This node represents both mux and config
16	of the pins in that group. The 'pins' selects the function mode(also named pin
17	mode) this pin can work on and the 'config' configures various pad settings
18	such as pull-up, multi drive, etc.
19	
20	Required properties for iomux controller:
21	- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22	- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
23	  configured in this periph mode. All the periph and bank need to be describe.
24	
25	How to create such array:
26	
27	Each column will represent the possible peripheral of the pinctrl
28	Each line will represent a pio bank
29	
30	Take an example on the 9260
31	Peripheral: 2 ( A and B)
32	Bank: 3 (A, B and C)
33	=>
34	
35	  /*    A         B     */
36	  0xffffffff 0xffc00c3b  /* pioA */
37	  0xffffffff 0x7fff3ccf  /* pioB */
38	  0xffffffff 0x007fffff  /* pioC */
39	
40	For each peripheral/bank we will descibe in a u32 if a pin can be
41	configured in it by putting 1 to the pin bit (1 << pin)
42	
43	Let's take the pioA on peripheral B
44	From the datasheet Table 10-2.
45	Peripheral B
46	PA0	MCDB0
47	PA1	MCCDB
48	PA2
49	PA3	MCDB3
50	PA4	MCDB2
51	PA5	MCDB1
52	PA6
53	PA7
54	PA8
55	PA9
56	PA10	ETX2
57	PA11	ETX3
58	PA12
59	PA13
60	PA14
61	PA15
62	PA16
63	PA17
64	PA18
65	PA19
66	PA20
67	PA21
68	PA22	ETXER
69	PA23	ETX2
70	PA24	ETX3
71	PA25	ERX2
72	PA26	ERX3
73	PA27	ERXCK
74	PA28	ECRS
75	PA29	ECOL
76	PA30	RXD4
77	PA31	TXD4
78	
79	=> 0xffc00c3b
80	
81	Required properties for pin configuration node:
82	- atmel,pins: 4 integers array, represents a group of pins mux and config
83	  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
84	  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
85	  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
86	
87	Bits used for CONFIG:
88	PULL_UP		(1 << 0): indicate this pin need a pull up.
89	MULTIDRIVE	(1 << 1): indicate this pin need to be configured as multidrive.
90	DEGLITCH	(1 << 2): indicate this pin need deglitch.
91	PULL_DOWN	(1 << 3): indicate this pin need a pull down.
92	DIS_SCHMIT	(1 << 4): indicate this pin need to disable schmit trigger.
93	DEBOUNCE	(1 << 16): indicate this pin need debounce.
94	DEBOUNCE_VAL	(0x3fff << 17): debounce val.
95	
96	NOTE:
97	Some requirements for using atmel,at91rm9200-pinctrl binding:
98	1. We have pin function node defined under at91 controller node to represent
99	   what pinmux functions this SoC supports.
100	2. The driver can use the function node's name and pin configuration node's
101	   name describe the pin function and group hierarchy.
102	   For example, Linux at91 pinctrl driver takes the function node's name
103	   as the function name and pin configuration node's name as group name to
104	   create the map table.
105	3. Each pin configuration node should have a phandle, devices can set pins
106	   configurations by referring to the phandle of that pin configuration node.
107	4. The gpio controller must be describe in the pinctrl simple-bus.
108	
109	Examples:
110	
111	pinctrl@fffff400 {
112		#address-cells = <1>;
113		#size-cells = <1>;
114		ranges;
115		compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
116		reg = <0xfffff400 0x600>;
117	
118		atmel,mux-mask = <
119		      /*    A         B     */
120		       0xffffffff 0xffc00c3b  /* pioA */
121		       0xffffffff 0x7fff3ccf  /* pioB */
122		       0xffffffff 0x007fffff  /* pioC */
123		      >;
124	
125		/* shared pinctrl settings */
126		dbgu {
127			pinctrl_dbgu: dbgu-0 {
128				atmel,pins =
129					<1 14 0x1 0x0	/* PB14 periph A */
130					 1 15 0x1 0x1>;	/* PB15 periph A with pullup */
131			};
132		};
133	};
134	
135	dbgu: serial@fffff200 {
136		compatible = "atmel,at91sam9260-usart";
137		reg = <0xfffff200 0x200>;
138		interrupts = <1 4 7>;
139		pinctrl-names = "default";
140		pinctrl-0 = <&pinctrl_dbgu>;
141		status = "disabled";
142	};
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