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Documentation / devicetree / bindings / sound / fsl,ssi.txt

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Based on kernel version 3.13. Page generated on 2014-01-20 22:01 EST.

1	Freescale Synchronous Serial Interface
3	The SSI is a serial device that communicates with audio codecs.  It can
4	be programmed in AC97, I2S, left-justified, or right-justified modes.
6	Required properties:
7	- compatible:       Compatible list, contains "fsl,ssi".
8	- cell-index:       The SSI, <0> = SSI1, <1> = SSI2, and so on.
9	- reg:              Offset and length of the register set for the device.
10	- interrupts:       <a b> where a is the interrupt number and b is a
11	                    field that represents an encoding of the sense and
12	                    level information for the interrupt.  This should be
13	                    encoded based on the information in section 2)
14	                    depending on the type of interrupt controller you
15	                    have.
16	- interrupt-parent: The phandle for the interrupt controller that
17	                    services interrupts for this device.
18	- fsl,mode:         The operating mode for the SSI interface.
19	                    "i2s-slave" - I2S mode, SSI is clock slave
20	                    "i2s-master" - I2S mode, SSI is clock master
21	                    "lj-slave" - left-justified mode, SSI is clock slave
22	                    "lj-master" - l.j. mode, SSI is clock master
23	                    "rj-slave" - right-justified mode, SSI is clock slave
24	                    "rj-master" - r.j., SSI is clock master
25	                    "ac97-slave" - AC97 mode, SSI is clock slave
26	                    "ac97-master" - AC97 mode, SSI is clock master
27	- fsl,playback-dma: Phandle to a node for the DMA channel to use for
28	                    playback of audio.  This is typically dictated by SOC
29	                    design.  See the notes below.
30	- fsl,capture-dma:  Phandle to a node for the DMA channel to use for
31	                    capture (recording) of audio.  This is typically dictated
32	                    by SOC design.  See the notes below.
33	- fsl,fifo-depth:   The number of elements in the transmit and receive FIFOs.
34	                    This number is the maximum allowed value for SFCSR[TFWM0].
35	- fsl,ssi-asynchronous:
36	                    If specified, the SSI is to be programmed in asynchronous
37	                    mode.  In this mode, pins SRCK, STCK, SRFS, and STFS must
38	                    all be connected to valid signals.  In synchronous mode,
39	                    SRCK and SRFS are ignored.  Asynchronous mode allows
40	                    playback and capture to use different sample sizes and
41	                    sample rates.  Some drivers may require that SRCK and STCK
42	                    be connected together, and SRFS and STFS be connected
43	                    together.  This would still allow different sample sizes,
44	                    but not different sample rates.
46	Required are also ac97 link bindings if ac97 is used. See
47	Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary
48	bindings.
50	Optional properties:
51	- codec-handle:     Phandle to a 'codec' node that defines an audio
52	                    codec connected to this SSI.  This node is typically
53	                    a child of an I2C or other control node.
54	- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
55			    filter the codec stream. This is necessary for some boards
56			    where an incompatible codec is connected to this SSI, e.g.
57			    on pca100 and pcm043.
58	- dmas:		    Generic dma devicetree binding as described in
59			    Documentation/devicetree/bindings/dma/dma.txt.
60	- dma-names:	    Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
61			    is not defined.
63	Child 'codec' node required properties:
64	- compatible:       Compatible list, contains the name of the codec
66	Child 'codec' node optional properties:
67	- clock-frequency:  The frequency of the input clock, which typically comes
68	                    from an on-board dedicated oscillator.
70	Notes on fsl,playback-dma and fsl,capture-dma:
72	On SOCs that have an SSI, specific DMA channels are hard-wired for playback
73	and capture.  On the MPC8610, for example, SSI1 must use DMA channel 0 for
74	playback and DMA channel 1 for capture.  SSI2 must use DMA channel 2 for
75	playback and DMA channel 3 for capture.  The developer can choose which
76	DMA controller to use, but the channels themselves are hard-wired.  The
77	purpose of these two properties is to represent this hardware design.
79	The device tree nodes for the DMA channels that are referenced by
80	"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
81	"fsl,ssi-dma-channel".  The SOC-specific compatible string (e.g.
82	"fsl,mpc8610-dma-channel") can remain.  If these nodes are left as
83	"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
84	drivers (fsldma) will attempt to use them, and it will conflict with the
85	sound drivers.
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