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Documentation / devicetree / bindings / usb / dwc3.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:11 EST.

1	synopsys DWC3 CORE
2	
3	DWC3- USB3 CONTROLLER
4	
5	Required properties:
6	 - compatible: must be "snps,dwc3"
7	 - reg : Address and length of the register set for the device
8	 - interrupts: Interrupts used by the dwc3 controller.
9	
10	Optional properties:
11	 - usb-phy : array of phandle for the PHY device.  The first element
12	   in the array is expected to be a handle to the USB2/HS PHY and
13	   the second element is expected to be a handle to the USB3/SS PHY
14	 - phys: from the *Generic PHY* bindings
15	 - phy-names: from the *Generic PHY* bindings
16	 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
17	 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
18	 - snps,disable_scramble_quirk: true when SW should disable data scrambling.
19		Only really useful for FPGA builds.
20	 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
21	 - snps,lpm-nyet-threshold: LPM NYET threshold
22	 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
23	 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
24	 - snps,req_p1p2p3_quirk: when set, the core will always request for
25				P1/P2/P3 transition sequence.
26	 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
27				amount of 8B10B errors occur.
28	 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
29				from P0 to P1/P2/P3.
30	 - snps,lfps_filter_quirk: when set core will filter LFPS reception.
31	 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
32				Polling LFPS after RX.Detect.
33	 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
34	 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
35				LTSSM during USB3 Compliance mode.
36	 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
37	 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
38	 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
39				utmi_l1_suspend_n, false when asserts utmi_sleep_n
40	 - snps,hird-threshold: HIRD threshold
41	
42	This is usually a subnode to DWC3 glue to which it is connected.
43	
44	dwc3@4a030000 {
45		compatible = "snps,dwc3";
46		reg = <0x4a030000 0xcfff>;
47		interrupts = <0 92 4>
48		usb-phy = <&usb2_phy>, <&usb3,phy>;
49		tx-fifo-resize;
50	};
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