Based on kernel version 4.2. Page generated on 2015-09-09 12:11 EST.
1 Tegra SOC USB PHY 2 3 The device node for Tegra SOC USB PHY: 4 5 Required properties : 6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". 7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain 8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is 9 tegra114, tegra124, tegra132, or tegra210. 10 - reg : Defines the following set of registers, in the order listed: 11 - The PHY's own register set. 12 Always present. 13 - The register set of the PHY containing the UTMI pad control registers. 14 Present if-and-only-if phy_type == utmi. 15 - phy_type : Should be one of "utmi", "ulpi" or "hsic". 16 - clocks : Defines the clocks listed in the clock-names property. 17 - clock-names : The following clock names must be present: 18 - reg: The clock needed to access the PHY's own registers. This is the 19 associated EHCI controller's clock. Always present. 20 - pll_u: PLL_U. Always present. 21 - timer: The timeout clock (clk_m). Present if phy_type == utmi. 22 - utmi-pads: The clock needed to access the UTMI pad control registers. 23 Present if phy_type == utmi. 24 - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). 25 Present if phy_type == ulpi, and ULPI link mode is in use. 26 - resets : Must contain an entry for each entry in reset-names. 27 See ../reset/reset.txt for details. 28 - reset-names : Must include the following entries: 29 - usb: The PHY's own reset signal. 30 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control 31 registers. Required even if phy_type == ulpi. 32 33 Required properties for phy_type == ulpi: 34 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 35 36 Required PHY timing params for utmi phy, for all chips: 37 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before 38 start of sync launches RxActive 39 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store 40 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait 41 before declare IDLE. 42 - nvidia,term-range-adj : Range adjusment on terminations 43 - Either one of the following for HS driver output control: 44 - nvidia,xcvr-setup : integer, uses the provided value. 45 - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read 46 from the on-chip fuses 47 If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. 48 - nvidia,xcvr-lsfslew : LS falling slew rate control. 49 - nvidia,xcvr-lsrslew : LS rising slew rate control. 50 51 Required PHY timing params for utmi phy, only on Tegra30 and above: 52 - nvidia,xcvr-hsslew : HS slew rate control. 53 - nvidia,hssquelch-level : HS squelch detector level. 54 - nvidia,hsdiscon-level : HS disconnect detector level. 55 56 Optional properties: 57 - nvidia,has-legacy-mode : boolean indicates whether this controller can 58 operate in legacy mode (as APX 2500 / 2600). In legacy mode some 59 registers are accessed through the APB_MISC base address instead of 60 the USB controller. 61 - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power 62 optimizations for the devices that are always connected. e.g. modem. 63 - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be 64 "host", "peripheral", or "otg". Defaults to "host" if not defined. 65 host means this is a host controller 66 peripheral means it is device controller 67 otg means it can operate as either ("on the go") 68 - nvidia,has-utmi-pad-registers : boolean indicates whether this controller 69 contains the UTMI pad control registers common to all USB controllers. 70 71 VBUS control (required for dr_mode == otg, optional for dr_mode == host): 72 - vbus-supply: regulator for VBUS