Based on kernel version 3.19. Page generated on 2015-02-13 21:19 EST.
1 Tegra SOC USB PHY 2 3 The device node for Tegra SOC USB PHY: 4 5 Required properties : 6 - compatible : Should be "nvidia,tegra<chip>-usb-phy". 7 - reg : Defines the following set of registers, in the order listed: 8 - The PHY's own register set. 9 Always present. 10 - The register set of the PHY containing the UTMI pad control registers. 11 Present if-and-only-if phy_type == utmi. 12 - phy_type : Should be one of "utmi", "ulpi" or "hsic". 13 - clocks : Defines the clocks listed in the clock-names property. 14 - clock-names : The following clock names must be present: 15 - reg: The clock needed to access the PHY's own registers. This is the 16 associated EHCI controller's clock. Always present. 17 - pll_u: PLL_U. Always present. 18 - timer: The timeout clock (clk_m). Present if phy_type == utmi. 19 - utmi-pads: The clock needed to access the UTMI pad control registers. 20 Present if phy_type == utmi. 21 - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). 22 Present if phy_type == ulpi, and ULPI link mode is in use. 23 - resets : Must contain an entry for each entry in reset-names. 24 See ../reset/reset.txt for details. 25 - reset-names : Must include the following entries: 26 - usb: The PHY's own reset signal. 27 - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control 28 registers. Required even if phy_type == ulpi. 29 30 Required properties for phy_type == ulpi: 31 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 32 33 Required PHY timing params for utmi phy, for all chips: 34 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before 35 start of sync launches RxActive 36 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store 37 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait 38 before declare IDLE. 39 - nvidia,term-range-adj : Range adjusment on terminations 40 - Either one of the following for HS driver output control: 41 - nvidia,xcvr-setup : integer, uses the provided value. 42 - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read 43 from the on-chip fuses 44 If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. 45 - nvidia,xcvr-lsfslew : LS falling slew rate control. 46 - nvidia,xcvr-lsrslew : LS rising slew rate control. 47 48 Required PHY timing params for utmi phy, only on Tegra30 and above: 49 - nvidia,xcvr-hsslew : HS slew rate control. 50 - nvidia,hssquelch-level : HS squelch detector level. 51 - nvidia,hsdiscon-level : HS disconnect detector level. 52 53 Optional properties: 54 - nvidia,has-legacy-mode : boolean indicates whether this controller can 55 operate in legacy mode (as APX 2500 / 2600). In legacy mode some 56 registers are accessed through the APB_MISC base address instead of 57 the USB controller. 58 - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power 59 optimizations for the devices that are always connected. e.g. modem. 60 - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be 61 "host", "peripheral", or "otg". Defaults to "host" if not defined. 62 host means this is a host controller 63 peripheral means it is device controller 64 otg means it can operate as either ("on the go") 65 - nvidia,has-utmi-pad-registers : boolean indicates whether this controller 66 contains the UTMI pad control registers common to all USB controllers. 67 68 VBUS control (required for dr_mode == otg, optional for dr_mode == host): 69 - vbus-supply: regulator for VBUS