Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 | ========================================================= NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU) ========================================================= The NVIDIA Tegra SoC includes various system PMUs to measure key performance metrics like memory bandwidth, latency, and utilization: * Scalable Coherency Fabric (SCF) * NVLink-C2C0 * NVLink-C2C1 * CNVLink * PCIE PMU Driver ---------- The PMUs in this document are based on ARM CoreSight PMU Architecture as described in document: ARM IHI 0091. Since this is a standard architecture, the PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes the available events and configuration of each PMU in sysfs. Please see the sections below to get the sysfs path of each PMU. Like other uncore PMU drivers, the driver provides "cpumask" sysfs attribute to show the CPU id used to handle the PMU event. There is also "associated_cpus" sysfs attribute, which contains a list of CPUs associated with the PMU instance. .. _SCF_PMU_Section: SCF PMU ------- The SCF PMU monitors system level cache events, CPU traffic, and strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU traffic coverage. The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>. Example usage: * Count event id 0x0 in socket 0:: perf stat -a -e nvidia_scf_pmu_0/event=0x0/ * Count event id 0x0 in socket 1:: perf stat -a -e nvidia_scf_pmu_1/event=0x0/ NVLink-C2C0 PMU -------------------- The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU varies dependent on the chip configuration: * NVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC. In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU. * NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected. In this config, the PMU captures read and relaxed ordered (RO) writes from PCIE device of the remote SoC. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU traffic coverage. The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_nvlink_c2c0_pmu_<socket-id>. Example usage: * Count event id 0x0 from the GPU/CPU connected with socket 0:: perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/ * Count event id 0x0 from the GPU/CPU connected with socket 1:: perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/ * Count event id 0x0 from the GPU/CPU connected with socket 2:: perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/ * Count event id 0x0 from the GPU/CPU connected with socket 3:: perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/ NVLink-C2C1 PMU ------------------- The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU traffic coverage. The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_nvlink_c2c1_pmu_<socket-id>. Example usage: * Count event id 0x0 from the GPU connected with socket 0:: perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/ * Count event id 0x0 from the GPU connected with socket 1:: perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/ * Count event id 0x0 from the GPU connected with socket 2:: perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/ * Count event id 0x0 from the GPU connected with socket 3:: perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/ CNVLink PMU --------------- The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets to local memory. For PCIE traffic, this PMU captures read and relaxed ordered (RO) write traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU traffic coverage. The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_cnvlink_pmu_<socket-id>. Each SoC socket can be connected to one or more sockets via CNVLink. The user can use "rem_socket" bitmap parameter to select the remote socket(s) to monitor. Each bit represents the socket number, e.g. "rem_socket=0xE" corresponds to socket 1 to 3. /sys/bus/event_sources/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket shows the valid bits that can be set in the "rem_socket" parameter. The PMU can not distinguish the remote traffic initiator, therefore it does not provide filter to select the traffic source to monitor. It reports combined traffic from remote GPU and PCIE devices. Example usage: * Count event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0:: perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/ * Count event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1:: perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/ * Count event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2:: perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/ * Count event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3:: perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/ PCIE PMU ------------ The PCIE PMU monitors all read/write traffic from PCIE root ports to local/remote memory. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU traffic coverage. The events and configuration options of this PMU device are described in sysfs, see /sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>. Each SoC socket can support multiple root ports. The user can use "root_port" bitmap parameter to select the port(s) to monitor, i.e. "root_port=0xF" corresponds to root port 0 to 3. /sys/bus/event_sources/devices/nvidia_pcie_pmu_<socket-id>/format/root_port shows the valid bits that can be set in the "root_port" parameter. Example usage: * Count event id 0x0 from root port 0 and 1 of socket 0:: perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/ * Count event id 0x0 from root port 0 and 1 of socket 1:: perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/ .. _NVIDIA_Uncore_PMU_Traffic_Coverage_Section: Traffic Coverage ---------------- The PMU traffic coverage may vary dependent on the chip configuration: * **NVIDIA Grace Hopper Superchip**: Hopper GPU is connected with Grace SoC. Example configuration with two Grace SoCs:: ********************************* ********************************* * SOCKET-A * * SOCKET-B * * * * * * :::::::: * * :::::::: * * : PCIE : * * : PCIE : * * :::::::: * * :::::::: * * | * * | * * | * * | * * ::::::: ::::::::: * * ::::::::: ::::::: * * : : : : * * : : : : * * : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : * * : : C2C : SoC : * * : SoC : C2C : : * * ::::::: ::::::::: * * ::::::::: ::::::: * * | | * * | | * * | | * * | | * * &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& * * & GMEM & & CMEM & * * & CMEM & & GMEM & * * &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& * * * * * ********************************* ********************************* GMEM = GPU Memory (e.g. HBM) CMEM = CPU Memory (e.g. LPDDR5X) | | Following table contains traffic coverage of Grace SoC PMU in socket-A: :: +--------------+-------+-----------+-----------+-----+----------+----------+ | | Source | + +-------+-----------+-----------+-----+----------+----------+ | Destination | |GPU ATS |GPU Not-ATS| | Socket-B | Socket-B | | |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2| | | |EGM | | | | | +==============+=======+===========+===========+=====+==========+==========+ | Local | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU | CNVLink | | SYSRAM/CMEM | PMU |PMU |PMU | PMU | | PMU | +--------------+-------+-----------+-----------+-----+----------+----------+ | Local GMEM | PCIE | N/A |NVLink-C2C1| SCF | SCF PMU | CNVLink | | | PMU | |PMU | PMU | | PMU | +--------------+-------+-----------+-----------+-----+----------+----------+ | Remote | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | | | SYSRAM/CMEM | PMU |PMU |PMU | PMU | N/A | N/A | | over CNVLink | | | | | | | +--------------+-------+-----------+-----------+-----+----------+----------+ | Remote GMEM | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | | | over CNVLink | PMU |PMU |PMU | PMU | N/A | N/A | +--------------+-------+-----------+-----------+-----+----------+----------+ PCIE1 traffic represents strongly ordered (SO) writes. PCIE2 traffic represents reads and relaxed ordered (RO) writes. * **NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected. Example configuration with two Grace SoCs:: ******************* ******************* * SOCKET-A * * SOCKET-B * * * * * * :::::::: * * :::::::: * * : PCIE : * * : PCIE : * * :::::::: * * :::::::: * * | * * | * * | * * | * * ::::::::: * * ::::::::: * * : : * * : : * * : Grace :<--------NVLink------->: Grace : * * : SoC : * C2C * : SoC : * * ::::::::: * * ::::::::: * * | * * | * * | * * | * * &&&&&&&& * * &&&&&&&& * * & CMEM & * * & CMEM & * * &&&&&&&& * * &&&&&&&& * * * * * ******************* ******************* GMEM = GPU Memory (e.g. HBM) CMEM = CPU Memory (e.g. LPDDR5X) | | Following table contains traffic coverage of Grace SoC PMU in socket-A: :: +-----------------+-----------+---------+----------+-------------+ | | Source | + +-----------+---------+----------+-------------+ | Destination | | | Socket-B | Socket-B | | | PCI R/W | CPU | CPU/PCIE1| PCIE2 | | | | | | | +=================+===========+=========+==========+=============+ | Local | PCIE PMU | SCF PMU | SCF PMU | NVLink-C2C0 | | SYSRAM/CMEM | | | | PMU | +-----------------+-----------+---------+----------+-------------+ | Remote | | | | | | SYSRAM/CMEM | PCIE PMU | SCF PMU | N/A | N/A | | over NVLink-C2C | | | | | +-----------------+-----------+---------+----------+-------------+ PCIE1 traffic represents strongly ordered (SO) writes. PCIE2 traffic represents reads and relaxed ordered (RO) writes. |