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Based on kernel version 4.8. Page generated on 2016-10-06 23:12 EST.

1	These properties are common to multiple MMC host controllers. Any host
2	that requires the respective functionality should implement them using
3	these definitions.
4	
5	Interpreted by the OF core:
6	- reg: Registers location and length.
7	- interrupts: Interrupts used by the MMC controller.
8	
9	Card detection:
10	If no property below is supplied, host native card detect is used.
11	Only one of the properties in this section should be supplied:
12	  - broken-cd: There is no card detection available; polling must be used.
13	  - cd-gpios: Specify GPIOs for card detection, see gpio binding
14	  - non-removable: non-removable slot (like eMMC); assume always present.
15	
16	Optional properties:
17	- bus-width: Number of data lines, can be <1>, <4>, or <8>.  The default
18	  will be <1> if the property is absent.
19	- wp-gpios: Specify GPIOs for write protection, see gpio binding
20	- cd-inverted: when present, polarity on the CD line is inverted. See the note
21	  below for the case, when a GPIO is used for the CD line
22	- wp-inverted: when present, polarity on the WP line is inverted. See the note
23	  below for the case, when a GPIO is used for the WP line
24	- disable-wp: When set no physical WP line is present. This property should
25	  only be specified when the controller has a dedicated write-protect
26	  detection logic. If a GPIO is always used for the write-protect detection
27	  logic it is sufficient to not specify wp-gpios property in the absence of a WP
28	  line.
29	- max-frequency: maximum operating clock frequency
30	- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
31	  this system, even if the controller claims it is.
32	- cap-sd-highspeed: SD high-speed timing is supported
33	- cap-mmc-highspeed: MMC high-speed timing is supported
34	- sd-uhs-sdr12: SD UHS SDR12 speed is supported
35	- sd-uhs-sdr25: SD UHS SDR25 speed is supported
36	- sd-uhs-sdr50: SD UHS SDR50 speed is supported
37	- sd-uhs-sdr104: SD UHS SDR104 speed is supported
38	- sd-uhs-ddr50: SD UHS DDR50 speed is supported
39	- cap-power-off-card: powering off the card is safe
40	- cap-mmc-hw-reset: eMMC hardware reset is supported
41	- cap-sdio-irq: enable SDIO IRQ signalling on this interface
42	- full-pwr-cycle: full power cycle of the card is supported
43	- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
44	- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
45	- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
46	- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
47	- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
48	- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
49	- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported
50	- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
51	  programmed with. Valid range: [0 .. 0xffff].
52	- no-sdio: controller is limited to send sdio cmd during initialization
53	- no-sd: controller is limited to send sd cmd during initialization
54	- no-mmc: controller is limited to send mmc cmd during initialization
55	
56	*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
57	polarity properties, we have to fix the meaning of the "normal" and "inverted"
58	line levels. We choose to follow the SDHCI standard, which specifies both those
59	lines as "active low." Therefore, using the "cd-inverted" property means, that
60	the CD line is active high, i.e. it is high, when a card is inserted. Similar
61	logic applies to the "wp-inverted" property.
62	
63	CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,
64	specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of
65	dedicated pins can be specified, using *-inverted properties. GPIO polarity can
66	also be specified using the OF_GPIO_ACTIVE_LOW flag. This creates an ambiguity
67	in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
68	This means, the two properties are "superimposed," for example leaving the
69	OF_GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted
70	property results in a double-inversion and actually means the "normal" line
71	polarity is in effect.
72	
73	Optional SDIO properties:
74	- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
75	- wakeup-source: Enables wake up of host system on SDIO IRQ assertion
76			 (Legacy property supported: "enable-sdio-wakeup")
77	
78	
79	MMC power sequences:
80	--------------------
81	
82	System on chip designs may specify a specific MMC power sequence. To
83	successfully detect an (e)MMC/SD/SDIO card, that power sequence must be
84	maintained while initializing the card.
85	
86	Optional property:
87	- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
88		for documentation of MMC power sequence bindings.
89	
90	
91	Use of Function subnodes
92	------------------------
93	
94	On embedded systems the cards connected to a host may need additional
95	properties. These can be specified in subnodes to the host controller node.
96	The subnodes are identified by the standard 'reg' property.
97	Which information exactly can be specified depends on the bindings for the
98	SDIO function driver for the subnode, as specified by the compatible string.
99	
100	Required host node properties when using function subnodes:
101	- #address-cells: should be one. The cell is the slot id.
102	- #size-cells: should be zero.
103	
104	Required function subnode properties:
105	- compatible: name of SDIO function following generic names recommended practice
106	- reg: Must contain the SDIO function number of the function this subnode
107	       describes. A value of 0 denotes the memory SD function, values from
108	       1 to 7 denote the SDIO functions.
109	
110	
111	Examples
112	--------
113	
114	Basic example:
115	
116	sdhci@ab000000 {
117		compatible = "sdhci";
118		reg = <0xab000000 0x200>;
119		interrupts = <23>;
120		bus-width = <4>;
121		cd-gpios = <&gpio 69 0>;
122		cd-inverted;
123		wp-gpios = <&gpio 70 0>;
124		max-frequency = <50000000>;
125		keep-power-in-suspend;
126		wakeup-source;
127		mmc-pwrseq = <&sdhci0_pwrseq>
128	}
129	
130	Example with sdio function subnode:
131	
132	mmc3: mmc@01c12000 {
133		#address-cells = <1>;
134		#size-cells = <0>;
135	
136		pinctrl-names = "default";
137		pinctrl-0 = <&mmc3_pins_a>;
138		vmmc-supply = <&reg_vmmc3>;
139		bus-width = <4>;
140		non-removable;
141		mmc-pwrseq = <&sdhci0_pwrseq>
142		status = "okay";
143	
144		brcmf: bcrmf@1 {
145			reg = <1>;
146			compatible = "brcm,bcm43xx-fmac";
147			interrupt-parent = <&pio>;
148			interrupts = <10 8>; /* PH10 / EINT10 */
149			interrupt-names = "host-wake";
150		};
151	};
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