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Documentation / devicetree / bindings / pinctrl / allwinner,sunxi-pinctrl.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Allwinner A1X Pin Controller
2	
3	The pins controlled by sunXi pin controller are organized in banks,
4	each bank has 32 pins.  Each pin has 7 multiplexing functions, with
5	the first two functions being GPIO in and out. The configuration on
6	the pins includes drive strength and pull-up.
7	
8	Required properties:
9	- compatible: Should be one of the following (depending on your SoC):
10	  "allwinner,sun4i-a10-pinctrl"
11	  "allwinner,sun5i-a10s-pinctrl"
12	  "allwinner,sun5i-a13-pinctrl"
13	  "allwinner,sun6i-a31-pinctrl"
14	  "allwinner,sun6i-a31s-pinctrl"
15	  "allwinner,sun6i-a31-r-pinctrl"
16	  "allwinner,sun7i-a20-pinctrl"
17	  "allwinner,sun8i-a23-pinctrl"
18	  "allwinner,sun8i-a23-r-pinctrl"
19	  "allwinner,sun8i-a33-pinctrl"
20	  "allwinner,sun9i-a80-pinctrl"
21	  "allwinner,sun9i-a80-r-pinctrl"
22	  "allwinner,sun8i-a83t-pinctrl"
23	  "allwinner,sun8i-a83t-r-pinctrl"
24	  "allwinner,sun8i-h3-pinctrl"
25	  "allwinner,sun8i-h3-r-pinctrl"
26	  "allwinner,sun8i-r40-pinctrl"
27	  "allwinner,sun50i-a64-pinctrl"
28	  "allwinner,sun50i-a64-r-pinctrl"
29	  "allwinner,sun50i-h5-pinctrl"
30	  "nextthing,gr8-pinctrl"
31	
32	- reg: Should contain the register physical address and length for the
33	  pin controller.
34	
35	- clocks: phandle to the clocks feeding the pin controller:
36	  - "apb": the gated APB parent clock
37	  - "hosc": the high frequency oscillator in the system
38	  - "losc": the low frequency oscillator in the system
39	
40	Note: For backward compatibility reasons, the hosc and losc clocks are only
41	required if you need to use the optional input-debounce property. Any new
42	device tree should set them.
43	
44	Optional properties:
45	  - input-debounce: Array of debouncing periods in microseconds. One period per
46	    irq bank found in the controller. 0 if no setup required.
47	
48	
49	Please refer to pinctrl-bindings.txt in this directory for details of the
50	common pinctrl bindings used by client devices.
51	
52	A pinctrl node should contain at least one subnodes representing the
53	pinctrl groups available on the machine. Each subnode will list the
54	pins it needs, and how they should be configured, with regard to muxer
55	configuration, drive strength and pullups. If one of these options is
56	not set, its actual value will be unspecified.
57	
58	This driver supports the generic pin multiplexing and configuration
59	bindings. For details on each properties, you can refer to
60	./pinctrl-bindings.txt.
61	
62	Required sub-node properties:
63	  - pins
64	  - function
65	
66	Optional sub-node properties:
67	  - bias-disable
68	  - bias-pull-up
69	  - bias-pull-down
70	  - drive-strength
71	
72	*** Deprecated pin configuration and multiplexing binding
73	
74	Required subnode-properties:
75	
76	- allwinner,pins: List of strings containing the pin name.
77	- allwinner,function: Function to mux the pins listed above to.
78	
79	Optional subnode-properties:
80	- allwinner,drive: Integer. Represents the current sent to the pin
81	    0: 10 mA
82	    1: 20 mA
83	    2: 30 mA
84	    3: 40 mA
85	- allwinner,pull: Integer.
86	    0: No resistor
87	    1: Pull-up resistor
88	    2: Pull-down resistor
89	
90	Examples:
91	
92	pio: pinctrl@01c20800 {
93		compatible = "allwinner,sun5i-a13-pinctrl";
94		reg = <0x01c20800 0x400>;
95		#address-cells = <1>;
96		#size-cells = <0>;
97	
98		uart1_pins_a: uart1@0 {
99			allwinner,pins = "PE10", "PE11";
100			allwinner,function = "uart1";
101			allwinner,drive = <0>;
102			allwinner,pull = <0>;
103		};
104	
105		uart1_pins_b: uart1@1 {
106			allwinner,pins = "PG3", "PG4";
107			allwinner,function = "uart1";
108			allwinner,drive = <0>;
109			allwinner,pull = <0>;
110		};
111	};
112	
113	
114	GPIO and interrupt controller
115	-----------------------------
116	
117	This hardware also acts as a GPIO controller and an interrupt
118	controller.
119	
120	Consumers that would want to refer to one or the other (or both)
121	should provide through the usual *-gpios and interrupts properties a
122	cell with 3 arguments, first the number of the bank, then the pin
123	inside that bank, and finally the flags for the GPIO/interrupts.
124	
125	Example:
126	
127	xio: gpio@38 {
128		compatible = "nxp,pcf8574a";
129		reg = <0x38>;
130	
131		gpio-controller;
132		#gpio-cells = <2>;
133	
134		interrupt-parent = <&pio>;
135		interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
136		interrupt-controller;
137		#interrupt-cells = <2>;
138	};
139	
140	reg_usb1_vbus: usb1-vbus {
141		compatible = "regulator-fixed";
142		regulator-name = "usb1-vbus";
143		regulator-min-microvolt = <5000000>;
144		regulator-max-microvolt = <5000000>;
145		gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
146	};
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