Based on kernel version 6.4.12
. Page generated on 2023-08-29 08:47 EST
.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | -------------------------------------------------------------------------- = Zynq UltraScale+ MPSoC and Versal reset driver binding = -------------------------------------------------------------------------- The Zynq UltraScale+ MPSoC and Versal has several different resets. See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information about zynqmp resets. Please also refer to reset.txt in this directory for common reset controller binding usage. Required Properties: - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform "xlnx,versal-reset" for Versal platform - #reset-cells: Specifies the number of cells needed to encode reset line, should be 1 ------- Example ------- firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; }; }; Specifying reset lines connected to IP modules ============================================== Device nodes that need access to reset lines should specify them as a reset phandle in their corresponding node as specified in reset.txt. For list of all valid reset indices for Zynq UltraScale+ MPSoC see <dt-bindings/reset/xlnx-zynqmp-resets.h> For list of all valid reset indices for Versal see <dt-bindings/reset/xlnx-versal-resets.h> Example: serdes: zynqmp_phy@fd400000 { ... resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; reset-names = "sata_rst"; ... }; |