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Documentation / arm / Samsung-S3C24XX / CPUfreq.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 08:59 EST.

1			S3C24XX CPUfreq support
2			=======================
3	
4	Introduction
5	------------
6	
7	 The S3C24XX series support a number of power saving systems, such as
8	 the ability to change the core, memory and peripheral operating
9	 frequencies. The core control is exported via the CPUFreq driver
10	 which has a number of different manual or automatic controls over the
11	 rate the core is running at.
12	
13	 There are two forms of the driver depending on the specific CPU and
14	 how the clocks are arranged. The first implementation used as single
15	 PLL to feed the ARM, memory and peripherals via a series of dividers
16	 and muxes and this is the implementation that is documented here. A
17	 newer version where there is a separate PLL and clock divider for the
18	 ARM core is available as a separate driver.
19	
20	
21	Layout
22	------
23	
24	 The code core manages the CPU specific drivers, any data that they
25	 need to register and the interface to the generic drivers/cpufreq
26	 system. Each CPU registers a driver to control the PLL, clock dividers
27	 and anything else associated with it. Any board that wants to use this
28	 framework needs to supply at least basic details of what is required.
29	
30	 The core registers with drivers/cpufreq at init time if all the data
31	 necessary has been supplied.
32	
33	
34	CPU support
35	-----------
36	
37	 The support for each CPU depends on the facilities provided by the
38	 SoC and the driver as each device has different PLL and clock chains
39	 associated with it.
40	
41	
42	Slow Mode
43	---------
44	
45	 The SLOW mode where the PLL is turned off altogether and the
46	 system is fed by the external crystal input is currently not
47	 supported.
48	
49	
50	sysfs
51	-----
52	
53	 The core code exports extra information via sysfs in the directory
54	 devices/system/cpu/cpu0/arch-freq.
55	
56	
57	Board Support
58	-------------
59	
60	 Each board that wants to use the cpufreq code must register some basic
61	 information with the core driver to provide information about what the
62	 board requires and any restrictions being placed on it.
63	
64	 The board needs to supply information about whether it needs the IO bank
65	 timings changing, any maximum frequency limits and information about the
66	 SDRAM refresh rate.
67	
68	
69	
70	
71	Document Author
72	---------------
73	
74	Ben Dooks, Copyright 2009 Simtec Electronics
75	Licensed under GPLv2
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