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Documentation / devicetree / bindings / arm / vexpress.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	ARM Versatile Express boards family
2	-----------------------------------
3	
4	ARM's Versatile Express platform consists of a motherboard and one
5	or more daughterboards (tiles). The motherboard provides a set of
6	peripherals. Processor and RAM "live" on the tiles.
7	
8	The motherboard and each core tile should be described by a separate
9	Device Tree source file, with the tile's description including
10	the motherboard file using a /include/ directive. As the motherboard
11	can be initialized in one of two different configurations ("memory
12	maps"), care must be taken to include the correct one.
13	
14	
15	Root node
16	---------
17	
18	Required properties in the root node:
19	- compatible value:
20		compatible = "arm,vexpress,<model>", "arm,vexpress";
21	  where <model> is the full tile model name (as used in the tile's
22	    Technical Reference Manual), eg.:
23	    - for Coretile Express A5x2 (V2P-CA5s):
24		compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
25	    - for Coretile Express A9x4 (V2P-CA9):
26		compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
27	  If a tile comes in several variants or can be used in more then one
28	  configuration, the compatible value should be:
29		compatible = "arm,vexpress,<model>,<variant>", \
30					"arm,vexpress,<model>", "arm,vexpress";
31	  eg:
32	    - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
33		compatible = "arm,vexpress,v2p-ca15,tc1", \
34					"arm,vexpress,v2p-ca15", "arm,vexpress";
35	    - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
36		compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
37					"arm,vexpress,v2f-2xv6", "arm,vexpress";
38	
39	Optional properties in the root node:
40	- tile model name (use name from the tile's Technical Reference
41	  Manual, eg. "V2P-CA5s")
42		model = "<model>";
43	- tile's HBI number (unique ARM's board model ID, visible on the
44	  PCB's silkscreen) in hexadecimal transcription:
45		arm,hbi = <0xhbi>
46	  eg:
47	  - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
48		arm,hbi = <0x191>;
49	  - Coretile Express A9x4 (V2P-CA9) HBI-0225:
50		arm,hbi = <0x225>;
51	
52	
53	CPU nodes
54	---------
55	
56	Top-level standard "cpus" node is required. It must contain a node
57	with device_type = "cpu" property for every available core, eg.:
58	
59		cpus {
60			#address-cells = <1>;
61			#size-cells = <0>;
62	
63			cpu@0 {
64				device_type = "cpu";
65				compatible = "arm,cortex-a5";
66				reg = <0>;
67			};
68		};
69	
70	
71	Configuration infrastructure
72	----------------------------
73	
74	The platform has an elaborated configuration system, consisting of
75	microcontrollers residing on the mother- and daughterboards known
76	as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
77	The controllers are responsible for the platform initialization
78	(reset generation, flash programming, FPGA bitfiles loading etc.)
79	but also control clock generators, voltage regulators, gather
80	environmental data like temperature, power consumption etc. Even
81	the video output switch (FPGA) is controlled that way.
82	
83	Nodes describing devices controlled by this infrastructure should
84	point at the bridge device node:
85	- bridge phandle:
86		arm,vexpress,config-bridge = <phandle>;
87	This property can be also defined in a parent node (eg. for a DCC)
88	and is effective for all children.
89	
90	
91	Platform topology
92	-----------------
93	
94	As Versatile Express can be configured in number of physically
95	different setups, the device tree should describe platform topology.
96	Root node and main motherboard node must define the following
97	property, describing physical location of the children nodes:
98	- site number:
99		arm,vexpress,site = <number>;
100	  where 0 means motherboard, 1 or 2 are daugtherboard sites,
101	  0xf means "master" site (site containing main CPU tile)
102	- when daughterboards are stacked on one site, their position
103	  in the stack be be described with:
104		arm,vexpress,position = <number>;
105	- when describing tiles consisting more than one DCC, its number
106	  can be described with:
107		arm,vexpress,dcc = <number>;
108	
109	Any of the numbers above defaults to zero if not defined in
110	the node or any of its parent.
111	
112	
113	Motherboard
114	-----------
115	
116	The motherboard description file provides a single "motherboard" node
117	using 2 address cells corresponding to the Static Memory Bus used
118	between the motherboard and the tile. The first cell defines the Chip
119	Select (CS) line number, the second cell address offset within the CS.
120	All interrupt lines between the motherboard and the tile are active
121	high and are described using single cell.
122	
123	Optional properties of the "motherboard" node:
124	- motherboard's memory map variant:
125		arm,v2m-memory-map = "<name>";
126	  where name is one of:
127	  - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
128	            referred to as "ARM Cortex-A Series memory map":
129		arm,v2m-memory-map = "rs1";
130	  When this property is missing, the motherboard is using the original
131	  memory map (also known as the "Legacy memory map", primarily used
132	  with the original CoreTile Express A9x4) with peripherals on CS7.
133	
134	Motherboard .dtsi files provide a set of labelled peripherals that
135	can be used to obtain required phandle in the tile's "aliases" node:
136	- UARTs, note that the numbers correspond to the physical connectors
137	  on the motherboard's back panel:
138		v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
139	- I2C controllers:
140		v2m_i2c_dvi and v2m_i2c_pcie
141	- SP804 timers:
142		v2m_timer01 and v2m_timer23
143	
144	The tile description should define a "smb" node, describing the
145	Static Memory Bus between the tile and motherboard. It must define
146	the following properties:
147	- "simple-bus" compatible value (to ensure creation of the children)
148		compatible = "simple-bus";
149	- mapping of the SMB CS/offset addresses into main address space:
150		#address-cells = <2>;
151		#size-cells = <1>;
152		ranges = <...>;
153	- interrupts mapping:
154		#interrupt-cells = <1>;
155		interrupt-map-mask = <0 0 63>;
156		interrupt-map = <...>;
157	
158	
159	Example of a VE tile description (simplified)
160	---------------------------------------------
161	
162	/dts-v1/;
163	
164	/ {
165		model = "V2P-CA5s";
166		arm,hbi = <0x225>;
167		arm,vexpress,site = <0xf>;
168		compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
169		interrupt-parent = <&gic>;
170		#address-cells = <1>;
171		#size-cells = <1>;
172	
173		chosen { };
174	
175		aliases {
176			serial0 = &v2m_serial0;
177		};
178	
179		cpus {
180			#address-cells = <1>;
181			#size-cells = <0>;
182	
183			cpu@0 {
184				device_type = "cpu";
185				compatible = "arm,cortex-a5";
186				reg = <0>;
187			};
188		};
189	
190		gic: interrupt-controller@2c001000 {
191			compatible = "arm,cortex-a9-gic";
192			#interrupt-cells = <3>;
193			#address-cells = <0>;
194			interrupt-controller;
195			reg = <0x2c001000 0x1000>,
196			      <0x2c000100 0x100>;
197		};
198	
199		dcc {
200			compatible = "simple-bus";
201			arm,vexpress,config-bridge = <&v2m_sysreg>;
202	
203			osc@0 {
204				compatible = "arm,vexpress-osc";
205			};
206		};
207	
208		smb {
209			compatible = "simple-bus";
210	
211			#address-cells = <2>;
212			#size-cells = <1>;
213			/* CS0 is visible at 0x08000000 */
214			ranges = <0 0 0x08000000 0x04000000>;
215	
216			#interrupt-cells = <1>;
217			interrupt-map-mask = <0 0 63>;
218			/* Active high IRQ 0 is connected to GIC's SPI0 */
219			interrupt-map = <0 0 0 &gic 0 0 4>;
220	
221			/include/ "vexpress-v2m-rs1.dtsi"
222		};
223	};
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