Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra186 (and later) Display Hub maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> properties: $nodename: pattern: "^display-hub@[0-9a-f]+$" compatible: enum: - nvidia,tegra186-display - nvidia,tegra194-display '#address-cells': enum: [ 1, 2 ] '#size-cells': enum: [ 1, 2 ] reg: maxItems: 1 interrupts: maxItems: 1 clocks: minItems: 2 maxItems: 3 clock-names: minItems: 2 maxItems: 3 resets: items: - description: display hub reset - description: window group 0 reset - description: window group 1 reset - description: window group 2 reset - description: window group 3 reset - description: window group 4 reset - description: window group 5 reset reset-names: items: - const: misc - const: wgrp0 - const: wgrp1 - const: wgrp2 - const: wgrp3 - const: wgrp4 - const: wgrp5 power-domains: maxItems: 1 ranges: maxItems: 1 patternProperties: "^display@[0-9a-f]+$": type: object allOf: - if: properties: compatible: contains: const: nvidia,tegra186-display then: properties: clocks: items: - description: display core clock - description: display stream compression clock - description: display hub clock clock-names: items: - const: disp - const: dsc - const: hub else: properties: clocks: items: - description: display core clock - description: display hub clock clock-names: items: - const: disp - const: hub additionalProperties: false required: - compatible - reg - clocks - clock-names - resets - reset-names - power-domains - "#address-cells" - "#size-cells" - ranges examples: - | #include <dt-bindings/clock/tegra186-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/memory/tegra186-mc.h> #include <dt-bindings/power/tegra186-powergate.h> #include <dt-bindings/reset/tegra186-reset.h> display-hub@15200000 { compatible = "nvidia,tegra186-display"; reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5"; clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; clock-names = "disp", "dsc", "hub"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; #address-cells = <1>; #size-cells = <1>; ranges = <0x15200000 0x15200000 0x40000>; display@15200000 { compatible = "nvidia,tegra186-dc"; reg = <0x15200000 0x10000>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; clock-names = "dc"; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <0>; }; display@15210000 { compatible = "nvidia,tegra186-dc"; reg = <0x15210000 0x10000>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; clock-names = "dc"; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <1>; }; display@15220000 { compatible = "nvidia,tegra186-dc"; reg = <0x15220000 0x10000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; clock-names = "dc"; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1>; nvidia,head = <2>; }; }; - | #include <dt-bindings/clock/tegra194-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/memory/tegra194-mc.h> #include <dt-bindings/power/tegra194-powergate.h> #include <dt-bindings/reset/tegra194-reset.h> display-hub@15200000 { compatible = "nvidia,tegra194-display"; reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", "wgrp3", "wgrp4", "wgrp5"; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; clock-names = "disp", "hub"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; #address-cells = <1>; #size-cells = <1>; ranges = <0x15200000 0x15200000 0x40000>; display@15200000 { compatible = "nvidia,tegra194-dc"; reg = <0x15200000 0x10000>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; clock-names = "dc"; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <0>; }; display@15210000 { compatible = "nvidia,tegra194-dc"; reg = <0x15210000 0x10000>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; clock-names = "dc"; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <1>; }; display@15220000 { compatible = "nvidia,tegra194-dc"; reg = <0x15220000 0x10000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; clock-names = "dc"; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <2>; }; display@15230000 { compatible = "nvidia,tegra194-dc"; reg = <0x15230000 0x10000>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; clock-names = "dc"; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <3>; }; }; |