Based on kernel version 4.3. Page generated on 2015-11-02 12:45 EST.
1 DesignWare HDMI bridge bindings 2 3 Required properties: 4 - compatible: platform specific such as: 5 * "snps,dw-hdmi-tx" 6 * "fsl,imx6q-hdmi" 7 * "fsl,imx6dl-hdmi" 8 * "rockchip,rk3288-dw-hdmi" 9 - reg: Physical base address and length of the controller's registers. 10 - interrupts: The HDMI interrupt number 11 - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, 12 as described in Documentation/devicetree/bindings/clock/clock-bindings.txt, 13 the clocks are soc specific, the clock-names should be "iahb", "isfr" 14 -port@[X]: SoC specific port nodes with endpoint definitions as defined 15 in Documentation/devicetree/bindings/media/video-interfaces.txt, 16 please refer to the SoC specific binding document: 17 * Documentation/devicetree/bindings/drm/imx/hdmi.txt 18 * Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt 19 20 Optional properties 21 - reg-io-width: the width of the reg:1,4, default set to 1 if not present 22 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 23 - clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec" 24 25 Example: 26 hdmi: hdmi@0120000 { 27 compatible = "fsl,imx6q-hdmi"; 28 reg = <0x00120000 0x9000>; 29 interrupts = <0 115 0x04>; 30 gpr = <&gpr>; 31 clocks = <&clks 123>, <&clks 124>; 32 clock-names = "iahb", "isfr"; 33 ddc-i2c-bus = <&i2c2>; 34 35 port@0 { 36 reg = <0>; 37 38 hdmi_mux_0: endpoint { 39 remote-endpoint = <&ipu1_di0_hdmi>; 40 }; 41 }; 42 43 port@1 { 44 reg = <1>; 45 46 hdmi_mux_1: endpoint { 47 remote-endpoint = <&ipu1_di1_hdmi>; 48 }; 49 }; 50 };