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Documentation / devicetree / bindings / i2c / i2c-ocores.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:09 EST.

1	Device tree configuration for i2c-ocores
2	
3	Required properties:
4	- compatible      : "opencores,i2c-ocores" or "aeroflexgaisler,i2cmst"
5	- reg             : bus address start and address range size of device
6	- interrupts      : interrupt number
7	- clocks          : handle to the controller clock; see the note below.
8	                    Mutually exclusive with opencores,ip-clock-frequency
9	- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
10	                    see the note below. Mutually exclusive with clocks
11	- #address-cells  : should be <1>
12	- #size-cells     : should be <0>
13	
14	Optional properties:
15	- clock-frequency : frequency of bus clock in Hz; see the note below.
16	                    Defaults to 100 KHz when the property is not specified
17	- reg-shift       : device register offsets are shifted by this value
18	- reg-io-width    : io register width in bytes (1, 2 or 4)
19	- regstep         : deprecated, use reg-shift above
20	
21	Note
22	clock-frequency property is meant to control the bus frequency for i2c bus
23	drivers, but it was incorrectly used to specify i2c controller input clock
24	frequency. So the following rules are set to fix this situation:
25	- if clock-frequency is present and neither opencores,ip-clock-frequency nor
26	  clocks are, then clock-frequency specifies i2c controller clock frequency.
27	  This is to keep backwards compatibility with setups using old DTB. i2c bus
28	  frequency is fixed at 100 KHz.
29	- if clocks is present it specifies i2c controller clock. clock-frequency
30	  property specifies i2c bus frequency.
31	- if opencores,ip-clock-frequency is present it specifies i2c controller
32	  clock frequency. clock-frequency property specifies i2c bus frequency.
33	
34	Examples:
35	
36		i2c0: ocores@a0000000 {
37			#address-cells = <1>;
38			#size-cells = <0>;
39			compatible = "opencores,i2c-ocores";
40			reg = <0xa0000000 0x8>;
41			interrupts = <10>;
42			opencores,ip-clock-frequency = <20000000>;
43	
44			reg-shift = <0>;	/* 8 bit registers */
45			reg-io-width = <1>;	/* 8 bit read/write */
46	
47			dummy@60 {
48				compatible = "dummy";
49				reg = <0x60>;
50			};
51		};
52	or
53		i2c0: ocores@a0000000 {
54			#address-cells = <1>;
55			#size-cells = <0>;
56			compatible = "opencores,i2c-ocores";
57			reg = <0xa0000000 0x8>;
58			interrupts = <10>;
59			clocks = <&osc>;
60			clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
61	
62			reg-shift = <0>;	/* 8 bit registers */
63			reg-io-width = <1>;	/* 8 bit read/write */
64	
65			dummy@60 {
66				compatible = "dummy";
67				reg = <0x60>;
68			};
69		};
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