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Documentation / devicetree / bindings / media / video-interfaces.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:09 EST.

1	Common bindings for video receiver and transmitter interfaces
2	
3	General concept
4	---------------
5	
6	Video data pipelines usually consist of external devices, e.g. camera sensors,
7	controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
8	video DMA engines and video data processors.
9	
10	SoC internal blocks are described by DT nodes, placed similarly to other SoC
11	blocks.  External devices are represented as child nodes of their respective
12	bus controller nodes, e.g. I2C.
13	
14	Data interfaces on all video devices are described by their child 'port' nodes.
15	Configuration of a port depends on other devices participating in the data
16	transfer and is described by 'endpoint' subnodes.
17	
18	device {
19		...
20		ports {
21			#address-cells = <1>;
22			#size-cells = <0>;
23	
24			port@0 {
25				...
26				endpoint@0 { ... };
27				endpoint@1 { ... };
28			};
29			port@1 { ... };
30		};
31	};
32	
33	If a port can be configured to work with more than one remote device on the same
34	bus, an 'endpoint' child node must be provided for each of them.  If more than
35	one port is present in a device node or there is more than one endpoint at a
36	port, or port node needs to be associated with a selected hardware interface,
37	a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
38	used.
39	
40	All 'port' nodes can be grouped under optional 'ports' node, which allows to
41	specify #address-cells, #size-cells properties independently for the 'port'
42	and 'endpoint' nodes and any child device nodes a device might have.
43	
44	Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
45	phandles.  An endpoint subnode of a device contains all properties needed for
46	configuration of this device for data exchange with other device.  In most
47	cases properties at the peer 'endpoint' nodes will be identical, however they
48	might need to be different when there is any signal modifications on the bus
49	between two devices, e.g. there are logic signal inverters on the lines.
50	
51	It is allowed for multiple endpoints at a port to be active simultaneously,
52	where supported by a device.  For example, in case where a data interface of
53	a device is partitioned into multiple data busses, e.g. 16-bit input port
54	divided into two separate ITU-R BT.656 8-bit busses.  In such case bus-width
55	and data-shift properties can be used to assign physical data lines to each
56	endpoint node (logical bus).
57	
58	
59	Required properties
60	-------------------
61	
62	If there is more than one 'port' or more than one 'endpoint' node or 'reg'
63	property is present in port and/or endpoint nodes the following properties
64	are required in a relevant parent node:
65	
66	 - #address-cells : number of cells required to define port/endpoint
67			    identifier, should be 1.
68	 - #size-cells    : should be zero.
69	
70	Optional endpoint properties
71	----------------------------
72	
73	- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
74	- slave-mode: a boolean property indicating that the link is run in slave mode.
75	  The default when this property is not specified is master mode. In the slave
76	  mode horizontal and vertical synchronization signals are provided to the
77	  slave device (data source) by the master device (data sink). In the master
78	  mode the data source device is also the source of the synchronization signals.
79	- bus-width: number of data lines actively used, valid for the parallel busses.
80	- data-shift: on the parallel data busses, if bus-width is used to specify the
81	  number of data lines, data-shift can be used to specify which data lines are
82	  used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
83	- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
84	- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
85	  Note, that if HSYNC and VSYNC polarities are not specified, embedded
86	  synchronization may be required, where supported.
87	- data-active: similar to HSYNC and VSYNC, specifies data line polarity.
88	- field-even-active: field signal level during the even field data transmission.
89	- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
90	  signal.
91	- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
92	  LOW/HIGH respectively.
93	- data-lanes: an array of physical data lane indexes. Position of an entry
94	  determines the logical lane number, while the value of an entry indicates
95	  physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
96	  "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
97	  This property is valid for serial busses only (e.g. MIPI CSI-2).
98	- clock-lanes: an array of physical clock lane indexes. Position of an entry
99	  determines the logical lane number, while the value of an entry indicates
100	  physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
101	  which places the clock lane on hardware lane 0. This property is valid for
102	  serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
103	  array contains only one entry.
104	- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
105	  clock mode.
106	- link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for
107	  instance, this is the actual frequency of the bus, not bits per clock per
108	  lane value. An array of 64-bit unsigned integers.
109	- lane-polarities: an array of polarities of the lanes starting from the clock
110	  lane and followed by the data lanes in the same order as in data-lanes.
111	  Valid values are 0 (normal) and 1 (inverted). The length of the array
112	  should be the combined length of data-lanes and clock-lanes properties.
113	  If the lane-polarities property is omitted, the value must be interpreted
114	  as 0 (normal). This property is valid for serial busses only.
115	
116	
117	Example
118	-------
119	
120	The example snippet below describes two data pipelines.  ov772x and imx074 are
121	camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
122	Both sensors are on the I2C control bus corresponding to the i2c0 controller
123	node.  ov772x sensor is linked directly to the ceu0 video host interface.
124	imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
125	(single) DMA engine writing captured data to memory.  ceu0 node has a single
126	'port' node which may indicate that at any time only one of the following data
127	pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
128	
129		ceu0: ceu@0xfe910000 {
130			compatible = "renesas,sh-mobile-ceu";
131			reg = <0xfe910000 0xa0>;
132			interrupts = <0x880>;
133	
134			mclk: master_clock {
135				compatible = "renesas,ceu-clock";
136				#clock-cells = <1>;
137				clock-frequency = <50000000>;	/* Max clock frequency */
138				clock-output-names = "mclk";
139			};
140	
141			port {
142				#address-cells = <1>;
143				#size-cells = <0>;
144	
145				/* Parallel bus endpoint */
146				ceu0_1: endpoint@1 {
147					reg = <1>;		/* Local endpoint # */
148					remote = <&ov772x_1_1>;	/* Remote phandle */
149					bus-width = <8>;	/* Used data lines */
150					data-shift = <2>;	/* Lines 9:2 are used */
151	
152					/* If hsync-active/vsync-active are missing,
153					   embedded BT.656 sync is used */
154					hsync-active = <0>;	/* Active low */
155					vsync-active = <0>;	/* Active low */
156					data-active = <1>;	/* Active high */
157					pclk-sample = <1>;	/* Rising */
158				};
159	
160				/* MIPI CSI-2 bus endpoint */
161				ceu0_0: endpoint@0 {
162					reg = <0>;
163					remote = <&csi2_2>;
164				};
165			};
166		};
167	
168		i2c0: i2c@0xfff20000 {
169			...
170			ov772x_1: camera@0x21 {
171				compatible = "ovti,ov772x";
172				reg = <0x21>;
173				vddio-supply = <&regulator1>;
174				vddcore-supply = <&regulator2>;
175	
176				clock-frequency = <20000000>;
177				clocks = <&mclk 0>;
178				clock-names = "xclk";
179	
180				port {
181					/* With 1 endpoint per port no need for addresses. */
182					ov772x_1_1: endpoint {
183						bus-width = <8>;
184						remote-endpoint = <&ceu0_1>;
185						hsync-active = <1>;
186						vsync-active = <0>; /* Who came up with an
187								       inverter here ?... */
188						data-active = <1>;
189						pclk-sample = <1>;
190					};
191				};
192			};
193	
194			imx074: camera@0x1a {
195				compatible = "sony,imx074";
196				reg = <0x1a>;
197				vddio-supply = <&regulator1>;
198				vddcore-supply = <&regulator2>;
199	
200				clock-frequency = <30000000>;	/* Shared clock with ov772x_1 */
201				clocks = <&mclk 0>;
202				clock-names = "sysclk";		/* Assuming this is the
203								   name in the datasheet */
204				port {
205					imx074_1: endpoint {
206						clock-lanes = <0>;
207						data-lanes = <1 2>;
208						remote-endpoint = <&csi2_1>;
209					};
210				};
211			};
212		};
213	
214		csi2: csi2@0xffc90000 {
215			compatible = "renesas,sh-mobile-csi2";
216			reg = <0xffc90000 0x1000>;
217			interrupts = <0x17a0>;
218			#address-cells = <1>;
219			#size-cells = <0>;
220	
221			port@1 {
222				compatible = "renesas,csi2c";	/* One of CSI2I and CSI2C. */
223				reg = <1>;			/* CSI-2 PHY #1 of 2: PHY_S,
224								   PHY_M has port address 0,
225								   is unused. */
226				csi2_1: endpoint {
227					clock-lanes = <0>;
228					data-lanes = <2 1>;
229					remote-endpoint = <&imx074_1>;
230				};
231			};
232			port@2 {
233				reg = <2>;			/* port 2: link to the CEU */
234	
235				csi2_2: endpoint {
236					remote-endpoint = <&ceu0_0>;
237				};
238			};
239		};
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