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Documentation / devicetree / bindings / memory-controllers / mvebu-devbus.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:37 EST.

1	Device tree bindings for MVEBU Device Bus controllers
2	
3	The Device Bus controller available in some Marvell's SoC allows to control
4	different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
5	The actual devices are instantiated from the child nodes of a Device Bus node.
6	
7	Required properties:
8	
9	 - compatible:          Armada 370/XP SoC are supported using the
10	                        "marvell,mvebu-devbus" compatible string.
11	
12	                        Orion5x SoC are supported using the
13	                        "marvell,orion-devbus" compatible string.
14	
15	 - reg:                 A resource specifier for the register space.
16	                        This is the base address of a chip select within
17				the controller's register space.
18	                        (see the example below)
19	
20	 - #address-cells:      Must be set to 1
21	 - #size-cells:         Must be set to 1
22	 - ranges:              Must be set up to reflect the memory layout with four
23	                        integer values for each chip-select line in use:
24	                        0 <physical address of mapping> <size>
25	
26	Optional properties:
27	
28	 - devbus,keep-config   This property can optionally be used to keep
29	                        using the timing parameters set by the
30	                        bootloader. It makes all the timing properties
31	                        described below unused.
32	
33	Timing properties for child nodes:
34	
35	Read parameters:
36	
37	 - devbus,turn-off-ps:  Defines the time during which the controller does not
38	                        drive the AD bus after the completion of a device read.
39	                        This prevents contentions on the Device Bus after a read
40	                        cycle from a slow device.
41	                        Mandatory, except if devbus,keep-config is used.
42	
43	 - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
44	                        Mandatory, except if devbus,keep-config is used.
45	
46	 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
47	                        to read data sample. This parameter is useful for
48	                        synchronous pipelined devices, where the address
49	                        precedes the read data by one or two cycles.
50	                        Mandatory, except if devbus,keep-config is used.
51	
52	 - devbus,acc-first-ps: Defines the time delay from the negation of
53	                        ALE[0] to the cycle that the first read data is sampled
54	                        by the controller.
55	                        Mandatory, except if devbus,keep-config is used.
56	
57	 - devbus,acc-next-ps:  Defines the time delay between the cycle that
58	                        samples data N and the cycle that samples data N+1
59	                        (in burst accesses).
60	                        Mandatory, except if devbus,keep-config is used.
61	
62	 - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
63				DEV_OEn assertion. If set to 0 (default),
64	                        DEV_OEn and DEV_CSn are asserted at the same cycle.
65	                        This parameter has no affect on <acc-first-ps> parameter
66	                        (no affect on first data sample). Set <rd-setup-ps>
67	                        to a value smaller than <acc-first-ps>.
68	                        Mandatory for "marvell,mvebu-devbus" compatible string,
69	                        except if devbus,keep-config is used.
70	
71	 - devbus,rd-hold-ps:   Defines the time between the last data sample to the
72				de-assertion of DEV_CSn. If set to 0 (default),
73				DEV_OEn and DEV_CSn are de-asserted at the same cycle
74				(the cycle of the last data sample).
75	                        This parameter has no affect on DEV_OEn de-assertion.
76	                        DEV_OEn is always de-asserted the next cycle after
77	                        last data sampled. Also this parameter has no
78	                        affect on <turn-off-ps> parameter.
79	                        Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
80	                        Mandatory for "marvell,mvebu-devbus" compatible string,
81	                        except if devbus,keep-config is used.
82	
83	Write parameters:
84	
85	 - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
86				to the DEV_WEn assertion.
87	                        Mandatory.
88	
89	 - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
90	                        A[2:0] and Data are kept valid as long as DEV_WEn
91	                        is active. This parameter defines the setup time of
92	                        address and data to DEV_WEn rise.
93	                        Mandatory.
94	
95	 - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
96	                        inactive (high) between data beats of a burst write.
97	                        DEV_A[2:0] and Data are kept valid (do not toggle) for
98	                        <wr-high-ps> - <tick> ps.
99				This parameter defines the hold time of address and
100				data after DEV_WEn rise.
101	                        Mandatory.
102	
103	 - devbus,sync-enable: Synchronous device enable.
104	                       1: True
105	                       0: False
106	                       Mandatory for "marvell,mvebu-devbus" compatible string,
107	                       except if devbus,keep-config is used.
108	
109	An example for an Armada XP GP board, with a 16 MiB NOR device as child
110	is showed below. Note that the Device Bus driver is in charge of allocating
111	the mbus address decoding window for each of its child devices.
112	The window is created using the chip select specified in the child
113	device node together with the base address and size specified in the ranges
114	property. For instance, in the example below the allocated decoding window
115	will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
116	for chip select 0 (a.k.a DEV_BOOTCS).
117	
118	This address window handling is done in this mvebu-devbus only as a temporary
119	solution. It will be removed when the support for mbus device tree binding is
120	added.
121	
122	The reg property implicitly specifies the chip select as this:
123	
124	  0x10400: DEV_BOOTCS
125	  0x10408: DEV_CS0
126	  0x10410: DEV_CS1
127	  0x10418: DEV_CS2
128	  0x10420: DEV_CS3
129	
130	Example:
131	
132		devbus-bootcs@d0010400 {
133			status = "okay";
134			ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
135			#address-cells = <1>;
136			#size-cells = <1>;
137	
138			/* Device Bus parameters are required */
139	
140			/* Read parameters */
141			devbus,bus-width    = <8>;
142			devbus,turn-off-ps  = <60000>;
143			devbus,badr-skew-ps = <0>;
144			devbus,acc-first-ps = <124000>;
145			devbus,acc-next-ps  = <248000>;
146			devbus,rd-setup-ps  = <0>;
147			devbus,rd-hold-ps   = <0>;
148	
149			/* Write parameters */
150			devbus,sync-enable = <0>;
151			devbus,wr-high-ps  = <60000>;
152			devbus,wr-low-ps   = <60000>;
153			devbus,ale-wr-ps   = <60000>;
154	
155			flash@0 {
156				compatible = "cfi-flash";
157	
158				/* 16 MiB */
159				reg = <0 0x1000000>;
160				bank-width = <2>;
161				#address-cells = <1>;
162				#size-cells = <1>;
163	
164				/*
165				 * We split the 16 MiB in two partitions,
166				 * just as an example.
167				 */
168				partition@0 {
169					label = "First";
170					reg = <0 0x800000>;
171				};
172	
173				partition@800000 {
174					label = "Second";
175					reg = <0x800000 0x800000>;
176				};
177			};
178		};
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