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Documentation / devicetree / bindings / memory-controllers / ti-aemif.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:37 EST.

1	* Device tree bindings for Texas instruments AEMIF controller
2	
3	The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
4	provide a glue-less interface to a variety of asynchronous memory devices like
5	ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
6	can be accessed at any given time via four chip selects with 64M byte access
7	per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
8	and Mobile SDR are not supported.
9	
10	Documentation:
11	Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12	OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13	Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
14	
15	Required properties:
16	
17	- compatible:		"ti,davinci-aemif"
18				"ti,keystone-aemif"
19				"ti,da850-aemif"
20	
21	- reg:			contains offset/length value for AEMIF control registers
22				space.
23	
24	- #address-cells:	Must be 2. The partition number has to be encoded in the
25				first address cell and it may accept values 0..N-1
26				(N - total number of partitions). It's recommended to
27				assign N-1 number for the control partition. The second
28				cell is the offset into the partition.
29	
30	- #size-cells:		Must be set to 1.
31	
32	- ranges:		Contains memory regions. There are two types of
33				ranges/partitions:
34				- CS-specific partition/range. If continuous, must be
35				set up to reflect the memory layout for 4 chipselects,
36				if not then additional range/partition can be added and
37				child device can select the proper one.
38				- control partition which is common for all CS
39				interfaces.
40	
41	- clocks:		the clock feeding the controller clock. Required only
42				if clock tree data present in device tree.
43				See clock-bindings.txt
44	
45	- clock-names:		clock name. It has to be "aemif". Required only if clock
46				tree data present in device tree, in another case don't
47				use it.
48				See clock-bindings.txt
49	
50	- clock-ranges:		Empty property indicating that child nodes can inherit
51				named clocks. Required only if clock tree data present
52				in device tree.
53				See clock-bindings.txt
54	
55	
56	Child chip-select (cs) nodes contain the memory devices nodes connected to
57	such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
58	There might be board specific devices like FPGAs.
59	
60	Required child cs node properties:
61	
62	- #address-cells:	Must be 2.
63	
64	- #size-cells:		Must be 1.
65	
66	- ranges:		Empty property indicating that child nodes can inherit
67				memory layout.
68	
69	- clock-ranges:		Empty property indicating that child nodes can inherit
70				named clocks. Required only if clock tree data present
71				in device tree.
72	
73	- ti,cs-chipselect:	number of chipselect. Indicates on the aemif driver
74				which chipselect is used for accessing the memory. For
75				compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
76				it can be in range [0-3]. For compatible
77				"ti,da850-aemif" range is [2-5].
78	
79	Optional child cs node properties:
80	
81	- ti,cs-bus-width:		width of the asynchronous device's data bus
82					8 or 16 if not preset 8
83	
84	- ti,cs-select-strobe-mode:	enable/disable select strobe mode
85					In select strobe mode chip select behaves as
86					the strobe and is active only during the strobe
87					period. If present then enable.
88	
89	- ti,cs-extended-wait-mode:	enable/disable extended wait mode
90					if set, the controller monitors the EMIFWAIT pin
91					mapped to that chip select to determine if the
92					device wants to extend the strobe period. If
93					present then enable.
94	
95	- ti,cs-min-turnaround-ns:	minimum turn around time, ns
96					Time between the end of one asynchronous memory
97					access and the start of another asynchronous
98					memory access. This delay is not incurred
99					between a read followed by read or a write
100					followed by a write to same chip select.
101	
102	- ti,cs-read-setup-ns:		read setup width, ns
103					Time between the beginning of a memory cycle
104					and the activation of read strobe.
105					Minimum value is 1 (0 treated as 1).
106	
107	- ti,cs-read-strobe-ns:		read strobe width, ns
108					Time between the activation and deactivation of
109					the read strobe.
110					Minimum value is 1 (0 treated as 1).
111	
112	- ti,cs-read-hold-ns:		read hold width, ns
113					Time between the deactivation of the read
114					strobe and the end of the cycle (which may be
115					either an address change or the deactivation of
116					the chip select signal.
117					Minimum value is 1 (0 treated as 1).
118	
119	- ti,cs-write-setup-ns:		write setup width, ns
120					Time between the beginning of a memory cycle
121					and the activation of write strobe.
122					Minimum value is 1 (0 treated as 1).
123	
124	- ti,cs-write-strobe-ns:	write strobe width, ns
125					Time between the activation and deactivation of
126					the write strobe.
127					Minimum value is 1 (0 treated as 1).
128	
129	- ti,cs-write-hold-ns:		write hold width, ns
130					Time between the deactivation of the write
131					strobe and the end of the cycle (which may be
132					either an address change or the deactivation of
133					the chip select signal.
134					Minimum value is 1 (0 treated as 1).
135	
136	If any of the above parameters are absent, current parameter value will be taken
137	from the corresponding HW reg.
138	
139	Example for aemif, davinci nand and nor flash chip select shown below.
140	
141	memory-controller@21000A00 {
142		compatible = "ti,davinci-aemif";
143		#address-cells = <2>;
144		#size-cells = <1>;
145		clocks = <&clkaemif 0>;
146		clock-names = "aemif";
147		clock-ranges;
148		reg = <0x21000A00 0x00000100>;
149		ranges = <0 0 0x70000000 0x10000000
150			  1 0 0x21000A00 0x00000100>;
151			  /*
152			   * Partition0: CS-specific memory range which is
153			   * implemented as continuous physical memory region
154			   * Partition1: control memory range
155			   */
156	
157		nand:cs2 {
158			#address-cells = <2>;
159			#size-cells = <1>;
160			clock-ranges;
161			ranges;
162	
163			ti,cs-chipselect = <2>;
164			/* all timings in nanoseconds */
165			ti,cs-min-turnaround-ns = <0>;
166			ti,cs-read-hold-ns = <7>;
167			ti,cs-read-strobe-ns = <42>;
168			ti,cs-read-setup-ns = <14>;
169			ti,cs-write-hold-ns = <7>;
170			ti,cs-write-strobe-ns = <42>;
171			ti,cs-write-setup-ns = <14>;
172	
173			nand@0,0x8000000 {
174				compatible = "ti,davinci-nand";
175				reg = <0 0x8000000 0x4000000
176				       1 0x0000000 0x0000100>;
177				/*
178				 * Partition0, offset 0x8000000, size 0x4000000
179				 * Partition1, offset 0x0000000, size 0x0000100
180				 */
181	
182				.. see davinci-nand.txt
183			};
184		};
185	
186		nor:cs0 {
187			#address-cells = <2>;
188			#size-cells = <1>;
189			clock-ranges;
190			ranges;
191	
192			ti,cs-chipselect = <0>;
193			/* all timings in nanoseconds */
194			ti,cs-min-turnaround-ns = <0>;
195			ti,cs-read-hold-ns = <8>;
196			ti,cs-read-strobe-ns = <40>;
197			ti,cs-read-setup-ns = <14>;
198			ti,cs-write-hold-ns = <7>;
199			ti,cs-write-strobe-ns = <40>;
200			ti,cs-write-setup-ns = <14>;
201			ti,cs-bus-width = <16>;
202	
203			flash@0,0x0000000 {
204				compatible = "cfi-flash";
205				reg = <0 0x0000000 0x4000000>;
206	
207				...
208			};
209		};
210	};
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