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Documentation / devicetree / bindings / pinctrl / pinctrl-single.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:01 EST.

1	One-register-per-pin type device tree based pinctrl driver
2	
3	Required properties:
4	- compatible : "pinctrl-single" or "pinconf-single".
5	  "pinctrl-single" means that pinconf isn't supported.
6	  "pinconf-single" means that generic pinconf is supported.
7	
8	- reg : offset and length of the register set for the mux registers
9	
10	- pinctrl-single,register-width : pinmux register access width in bits
11	
12	- pinctrl-single,function-mask : mask of allowed pinmux function bits
13	  in the pinmux register
14	
15	Optional properties:
16	- pinctrl-single,function-off : function off mode for disabled state if
17	  available and same for all registers; if not specified, disabling of
18	  pin functions is ignored
19	
20	- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
21	  more than one pin, for which "pinctrl-single,function-mask" property specifies
22	 position mask of pin.
23	
24	- pinctrl-single,drive-strength : array of value that are used to configure
25	  drive strength in the pinmux register. They're value of drive strength
26	  current and drive strength mask.
27	
28			/* drive strength current, mask */
29			pinctrl-single,power-source = <0x30 0xf0>;
30	
31	- pinctrl-single,bias-pullup : array of value that are used to configure the
32	  input bias pullup in the pinmux register.
33	
34			/* input, enabled pullup bits, disabled pullup bits, mask */
35			pinctrl-single,bias-pullup = <0 1 0 1>;
36	
37	- pinctrl-single,bias-pulldown : array of value that are used to configure the
38	  input bias pulldown in the pinmux register.
39	
40			/* input, enabled pulldown bits, disabled pulldown bits, mask */
41			pinctrl-single,bias-pulldown = <2 2 0 2>;
42	
43	  * Two bits to control input bias pullup and pulldown: User should use
44	    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
45	    pullup, and the other one bit means pulldown.
46	  * Three bits to control input bias enable, pullup and pulldown. User should
47	    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
48	    enable bit should be included in pullup or pulldown bits.
49	  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
50	    pinctrl-single,bias-disable. Because pinctrl single driver could implement
51	    it by calling pulldown, pullup disabled.
52	
53	- pinctrl-single,input-schmitt : array of value that are used to configure
54	  input schmitt in the pinmux register. In some silicons, there're two input
55	  schmitt value (rising-edge & falling-edge) in the pinmux register.
56	
57			/* input schmitt value, mask */
58			pinctrl-single,input-schmitt = <0x30 0x70>;
59	
60	- pinctrl-single,input-schmitt-enable : array of value that are used to
61	  configure input schmitt enable or disable in the pinmux register.
62	
63			/* input, enable bits, disable bits, mask */
64			pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
65	
66	- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
67	  range. They're value of subnode phandle, pin base in pinctrl device, pin
68	  number in this range, GPIO function value of this GPIO range.
69	  The number of parameters is depend on #pinctrl-single,gpio-range-cells
70	  property.
71	
72			/* pin base, nr pins & gpio function */
73			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
74	
75	- interrupt-controller : standard interrupt controller binding if using
76	  interrupts for wake-up events for example. In this case pinctrl-single
77	  is set up as a chained interrupt controller and the wake-up interrupts
78	  can be requested by the drivers using request_irq().
79	
80	- #interrupt-cells : standard interrupt binding if using interrupts
81	
82	This driver assumes that there is only one register for each pin (unless the
83	pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
84	specified in the pinctrl-bindings.txt document in this directory.
85	
86	The pin configuration nodes for pinctrl-single are specified as pinctrl
87	register offset and value pairs using pinctrl-single,pins. Only the bits
88	specified in pinctrl-single,function-mask are updated. For example, setting
89	a pin for a device could be done with:
90	
91		pinctrl-single,pins = <0xdc 0x118>;
92	
93	Where 0xdc is the offset from the pinctrl register base address for the
94	device pinctrl register, and 0x118 contains the desired value of the
95	pinctrl register. See the device example and static board pins example
96	below for more information.
97	
98	In case when one register changes more than one pin's mux the
99	pinctrl-single,bits need to be used which takes three parameters:
100	
101		pinctrl-single,bits = <0xdc 0x18, 0xff>;
102	
103	Where 0xdc is the offset from the pinctrl register base address for the
104	device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
105	be used when applying this change to the register.
106	
107	
108	Optional sub-node: In case some pins could be configured as GPIO in the pinmux
109	register, those pins could be defined as a GPIO range. This sub-node is required
110	by pinctrl-single,gpio-range property.
111	
112	Required properties in sub-node:
113	- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
114	  pinctrl-single,gpio-range property.
115	
116		range: gpio-range {
117			#pinctrl-single,gpio-range-cells = <3>;
118		};
119	
120	
121	Example:
122	
123	/* SoC common file */
124	
125	/* first controller instance for pins in core domain */
126	pmx_core: pinmux@4a100040 {
127		compatible = "pinctrl-single";
128		reg = <0x4a100040 0x0196>;
129		#address-cells = <1>;
130		#size-cells = <0>;
131		#interrupt-cells = <1>;
132		interrupt-controller;
133		pinctrl-single,register-width = <16>;
134		pinctrl-single,function-mask = <0xffff>;
135	};
136	
137	/* second controller instance for pins in wkup domain */
138	pmx_wkup: pinmux@4a31e040 {
139		compatible = "pinctrl-single";
140		reg = <0x4a31e040 0x0038>;
141		#address-cells = <1>;
142		#size-cells = <0>;
143		#interrupt-cells = <1>;
144		interrupt-controller;
145		pinctrl-single,register-width = <16>;
146		pinctrl-single,function-mask = <0xffff>;
147	};
148	
149	control_devconf0: pinmux@48002274 {
150		compatible = "pinctrl-single";
151		reg = <0x48002274 4>;	/* Single register */
152		#address-cells = <1>;
153		#size-cells = <0>;
154		pinctrl-single,bit-per-mux;
155		pinctrl-single,register-width = <32>;
156		pinctrl-single,function-mask = <0x5F>;
157	};
158	
159	/* third controller instance for pins in gpio domain */
160	pmx_gpio: pinmux@d401e000 {
161		compatible = "pinconf-single";
162		reg = <0xd401e000 0x0330>;
163		#address-cells = <1>;
164		#size-cells = <1>;
165		ranges;
166	
167		pinctrl-single,register-width = <32>;
168		pinctrl-single,function-mask = <7>;
169	
170		/* sparse GPIO range could be supported */
171		pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
172					&range 12 1 0 &range 13 29 1
173					&range 43 1 0 &range 44 49 1
174					&range 94 1 1 &range 96 2 1>;
175	
176		range: gpio-range {
177			#pinctrl-single,gpio-range-cells = <3>;
178		};
179	};
180	
181	
182	/* board specific .dts file */
183	
184	&pmx_core {
185	
186		/*
187		 * map all board specific static pins enabled by the pinctrl driver
188		 * itself during the boot (or just set them up in the bootloader)
189		 */
190		pinctrl-names = "default";
191		pinctrl-0 = <&board_pins>;
192	
193		board_pins: pinmux_board_pins {
194			pinctrl-single,pins = <
195				0x6c 0xf
196				0x6e 0xf
197				0x70 0xf
198				0x72 0xf
199			>;
200		};
201	
202		uart0_pins: pinmux_uart0_pins {
203			pinctrl-single,pins = <
204				0x208 0		/* UART0_RXD (IOCFG138) */
205				0x20c 0		/* UART0_TXD (IOCFG139) */
206			>;
207			pinctrl-single,bias-pulldown = <0 2 2>;
208			pinctrl-single,bias-pullup = <0 1 1>;
209		};
210	
211		/* map uart2 pins */
212		uart2_pins: pinmux_uart2_pins {
213			pinctrl-single,pins = <
214				0xd8 0x118
215				0xda 0
216				0xdc 0x118
217				0xde 0
218			>;
219		};
220	};
221	
222	&control_devconf0 {
223		mcbsp1_pins: pinmux_mcbsp1_pins {
224			pinctrl-single,bits = <
225				0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
226			>;
227		};
228	
229		mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
230			pinctrl-single,bits = <
231				0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
232			>;
233		};
234	
235	};
236	
237	&uart1 {
238	       pinctrl-names = "default";
239	       pinctrl-0 = <&uart0_pins>;
240	};
241	
242	&uart2 {
243	       pinctrl-names = "default";
244	       pinctrl-0 = <&uart2_pins>;
245	};
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