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Documentation / devicetree / bindings / pinctrl / pinctrl-single.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:01 EST.

1	One-register-per-pin type device tree based pinctrl driver
2	
3	Required properties:
4	- compatible : "pinctrl-single" or "pinconf-single".
5	  "pinctrl-single" means that pinconf isn't supported.
6	  "pinconf-single" means that generic pinconf is supported.
7	
8	- reg : offset and length of the register set for the mux registers
9	
10	- pinctrl-single,register-width : pinmux register access width in bits
11	
12	- pinctrl-single,function-mask : mask of allowed pinmux function bits
13	  in the pinmux register
14	
15	Optional properties:
16	- pinctrl-single,function-off : function off mode for disabled state if
17	  available and same for all registers; if not specified, disabling of
18	  pin functions is ignored
19	
20	- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
21	  more than one pin, for which "pinctrl-single,function-mask" property specifies
22	 position mask of pin.
23	
24	- pinctrl-single,drive-strength : array of value that are used to configure
25	  drive strength in the pinmux register. They're value of drive strength
26	  current and drive strength mask.
27	
28			/* drive strength current, mask */
29			pinctrl-single,power-source = <0x30 0xf0>;
30	
31	- pinctrl-single,bias-pullup : array of value that are used to configure the
32	  input bias pullup in the pinmux register.
33	
34			/* input, enabled pullup bits, disabled pullup bits, mask */
35			pinctrl-single,bias-pullup = <0 1 0 1>;
36	
37	- pinctrl-single,bias-pulldown : array of value that are used to configure the
38	  input bias pulldown in the pinmux register.
39	
40			/* input, enabled pulldown bits, disabled pulldown bits, mask */
41			pinctrl-single,bias-pulldown = <2 2 0 2>;
42	
43	  * Two bits to control input bias pullup and pulldown: User should use
44	    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
45	    pullup, and the other one bit means pulldown.
46	  * Three bits to control input bias enable, pullup and pulldown. User should
47	    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
48	    enable bit should be included in pullup or pulldown bits.
49	  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
50	    pinctrl-single,bias-disable. Because pinctrl single driver could implement
51	    it by calling pulldown, pullup disabled.
52	
53	- pinctrl-single,input-schmitt : array of value that are used to configure
54	  input schmitt in the pinmux register. In some silicons, there're two input
55	  schmitt value (rising-edge & falling-edge) in the pinmux register.
56	
57			/* input schmitt value, mask */
58			pinctrl-single,input-schmitt = <0x30 0x70>;
59	
60	- pinctrl-single,input-schmitt-enable : array of value that are used to
61	  configure input schmitt enable or disable in the pinmux register.
62	
63			/* input, enable bits, disable bits, mask */
64			pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
65	
66	- pinctrl-single,low-power-mode : array of value that are used to configure
67	  low power mode of this pin. For some silicons, the low power mode will
68	  control the output of the pin when the pad including the pin enter low
69	  power mode.
70			/* low power mode value, mask */
71			pinctrl-single,low-power-mode = <0x288 0x388>;
72	
73	- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
74	  range. They're value of subnode phandle, pin base in pinctrl device, pin
75	  number in this range, GPIO function value of this GPIO range.
76	  The number of parameters is depend on #pinctrl-single,gpio-range-cells
77	  property.
78	
79			/* pin base, nr pins & gpio function */
80			pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
81	
82	- interrupt-controller : standard interrupt controller binding if using
83	  interrupts for wake-up events for example. In this case pinctrl-single
84	  is set up as a chained interrupt controller and the wake-up interrupts
85	  can be requested by the drivers using request_irq().
86	
87	- #interrupt-cells : standard interrupt binding if using interrupts
88	
89	This driver assumes that there is only one register for each pin (unless the
90	pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
91	specified in the pinctrl-bindings.txt document in this directory.
92	
93	The pin configuration nodes for pinctrl-single are specified as pinctrl
94	register offset and value pairs using pinctrl-single,pins. Only the bits
95	specified in pinctrl-single,function-mask are updated. For example, setting
96	a pin for a device could be done with:
97	
98		pinctrl-single,pins = <0xdc 0x118>;
99	
100	Where 0xdc is the offset from the pinctrl register base address for the
101	device pinctrl register, and 0x118 contains the desired value of the
102	pinctrl register. See the device example and static board pins example
103	below for more information.
104	
105	In case when one register changes more than one pin's mux the
106	pinctrl-single,bits need to be used which takes three parameters:
107	
108		pinctrl-single,bits = <0xdc 0x18 0xff>;
109	
110	Where 0xdc is the offset from the pinctrl register base address for the
111	device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
112	be used when applying this change to the register.
113	
114	
115	Optional sub-node: In case some pins could be configured as GPIO in the pinmux
116	register, those pins could be defined as a GPIO range. This sub-node is required
117	by pinctrl-single,gpio-range property.
118	
119	Required properties in sub-node:
120	- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
121	  pinctrl-single,gpio-range property.
122	
123		range: gpio-range {
124			#pinctrl-single,gpio-range-cells = <3>;
125		};
126	
127	
128	Example:
129	
130	/* SoC common file */
131	
132	/* first controller instance for pins in core domain */
133	pmx_core: pinmux@4a100040 {
134		compatible = "pinctrl-single";
135		reg = <0x4a100040 0x0196>;
136		#address-cells = <1>;
137		#size-cells = <0>;
138		#interrupt-cells = <1>;
139		interrupt-controller;
140		pinctrl-single,register-width = <16>;
141		pinctrl-single,function-mask = <0xffff>;
142	};
143	
144	/* second controller instance for pins in wkup domain */
145	pmx_wkup: pinmux@4a31e040 {
146		compatible = "pinctrl-single";
147		reg = <0x4a31e040 0x0038>;
148		#address-cells = <1>;
149		#size-cells = <0>;
150		#interrupt-cells = <1>;
151		interrupt-controller;
152		pinctrl-single,register-width = <16>;
153		pinctrl-single,function-mask = <0xffff>;
154	};
155	
156	control_devconf0: pinmux@48002274 {
157		compatible = "pinctrl-single";
158		reg = <0x48002274 4>;	/* Single register */
159		#address-cells = <1>;
160		#size-cells = <0>;
161		pinctrl-single,bit-per-mux;
162		pinctrl-single,register-width = <32>;
163		pinctrl-single,function-mask = <0x5F>;
164	};
165	
166	/* third controller instance for pins in gpio domain */
167	pmx_gpio: pinmux@d401e000 {
168		compatible = "pinconf-single";
169		reg = <0xd401e000 0x0330>;
170		#address-cells = <1>;
171		#size-cells = <1>;
172		ranges;
173	
174		pinctrl-single,register-width = <32>;
175		pinctrl-single,function-mask = <7>;
176	
177		/* sparse GPIO range could be supported */
178		pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
179					&range 12 1 0 &range 13 29 1
180					&range 43 1 0 &range 44 49 1
181					&range 94 1 1 &range 96 2 1>;
182	
183		range: gpio-range {
184			#pinctrl-single,gpio-range-cells = <3>;
185		};
186	};
187	
188	
189	/* board specific .dts file */
190	
191	&pmx_core {
192	
193		/*
194		 * map all board specific static pins enabled by the pinctrl driver
195		 * itself during the boot (or just set them up in the bootloader)
196		 */
197		pinctrl-names = "default";
198		pinctrl-0 = <&board_pins>;
199	
200		board_pins: pinmux_board_pins {
201			pinctrl-single,pins = <
202				0x6c 0xf
203				0x6e 0xf
204				0x70 0xf
205				0x72 0xf
206			>;
207		};
208	
209		uart0_pins: pinmux_uart0_pins {
210			pinctrl-single,pins = <
211				0x208 0		/* UART0_RXD (IOCFG138) */
212				0x20c 0		/* UART0_TXD (IOCFG139) */
213			>;
214			pinctrl-single,bias-pulldown = <0 2 2>;
215			pinctrl-single,bias-pullup = <0 1 1>;
216		};
217	
218		/* map uart2 pins */
219		uart2_pins: pinmux_uart2_pins {
220			pinctrl-single,pins = <
221				0xd8 0x118
222				0xda 0
223				0xdc 0x118
224				0xde 0
225			>;
226		};
227	};
228	
229	&control_devconf0 {
230		mcbsp1_pins: pinmux_mcbsp1_pins {
231			pinctrl-single,bits = <
232				0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
233			>;
234		};
235	
236		mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
237			pinctrl-single,bits = <
238				0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
239			>;
240		};
241	
242	};
243	
244	&uart1 {
245	       pinctrl-names = "default";
246	       pinctrl-0 = <&uart0_pins>;
247	};
248	
249	&uart2 {
250	       pinctrl-names = "default";
251	       pinctrl-0 = <&uart2_pins>;
252	};
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