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Documentation / devicetree / bindings / sound / fsl,spdif.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:01 EST.

1	Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
2	
3	The Freescale S/PDIF audio block is a stereo transceiver that allows the
4	processor to receive and transmit digital audio via an coaxial cable or
5	a fibre cable.
6	
7	Required properties:
8	
9	  - compatible : Compatible list, must contain "fsl,imx35-spdif".
10	
11	  - reg : Offset and length of the register set for the device.
12	
13	  - interrupts : Contains the spdif interrupt.
14	
15	  - dmas : Generic dma devicetree binding as described in
16	  Documentation/devicetree/bindings/dma/dma.txt.
17	
18	  - dma-names : Two dmas have to be defined, "tx" and "rx".
19	
20	  - clocks : Contains an entry for each entry in clock-names.
21	
22	  - clock-names : Includes the following entries:
23		"core"		The core clock of spdif controller
24		"rxtx<0-7>"	Clock source list for tx and rx clock.
25				This clock list should be identical to
26				the source list connecting to the spdif
27				clock mux in "SPDIF Transceiver Clock
28				Diagram" of SoC reference manual. It
29				can also be referred to TxClk_Source
30				bit of register SPDIF_STC.
31	
32	   - big-endian : If this property is absent, the native endian mode will
33	   be in use as default, or the big endian mode will be in use for all the
34	   device registers.
35	
36	Example:
37	
38	spdif: spdif@02004000 {
39		compatible = "fsl,imx35-spdif";
40		reg = <0x02004000 0x4000>;
41		interrupts = <0 52 0x04>;
42		dmas = <&sdma 14 18 0>,
43		       <&sdma 15 18 0>;
44		dma-names = "rx", "tx";
45	
46		clocks = <&clks 197>, <&clks 3>,
47		       <&clks 197>, <&clks 107>,
48		       <&clks 0>, <&clks 118>,
49		       <&clks 62>, <&clks 139>,
50		       <&clks 0>;
51		clock-names = "core", "rxtx0",
52			"rxtx1", "rxtx2",
53			"rxtx3", "rxtx4",
54			"rxtx5", "rxtx6",
55			"rxtx7";
56	
57		big-endian;
58		status = "okay";
59	};
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