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Based on kernel version 4.7.2. Page generated on 2016-08-22 22:46 EST.

1	Linux Kernel Makefiles
2	
3	This document describes the Linux kernel Makefiles.
4	
5	=== Table of Contents
6	
7		=== 1 Overview
8		=== 2 Who does what
9		=== 3 The kbuild files
10		   --- 3.1 Goal definitions
11		   --- 3.2 Built-in object goals - obj-y
12		   --- 3.3 Loadable module goals - obj-m
13		   --- 3.4 Objects which export symbols
14		   --- 3.5 Library file goals - lib-y
15		   --- 3.6 Descending down in directories
16		   --- 3.7 Compilation flags
17		   --- 3.8 Command line dependency
18		   --- 3.9 Dependency tracking
19		   --- 3.10 Special Rules
20		   --- 3.11 $(CC) support functions
21		   --- 3.12 $(LD) support functions
22	
23		=== 4 Host Program support
24		   --- 4.1 Simple Host Program
25		   --- 4.2 Composite Host Programs
26		   --- 4.3 Using C++ for host programs
27		   --- 4.4 Controlling compiler options for host programs
28		   --- 4.5 When host programs are actually built
29		   --- 4.6 Using hostprogs-$(CONFIG_FOO)
30	
31		=== 5 Kbuild clean infrastructure
32	
33		=== 6 Architecture Makefiles
34		   --- 6.1 Set variables to tweak the build to the architecture
35		   --- 6.2 Add prerequisites to archheaders:
36		   --- 6.3 Add prerequisites to archprepare:
37		   --- 6.4 List directories to visit when descending
38		   --- 6.5 Architecture-specific boot images
39		   --- 6.6 Building non-kbuild targets
40		   --- 6.7 Commands useful for building a boot image
41		   --- 6.8 Custom kbuild commands
42		   --- 6.9 Preprocessing linker scripts
43		   --- 6.10 Generic header files
44	
45		=== 7 Kbuild syntax for exported headers
46			--- 7.1 header-y
47			--- 7.2 genhdr-y
48			--- 7.3 destination-y
49			--- 7.4 generic-y
50	
51		=== 8 Kbuild Variables
52		=== 9 Makefile language
53		=== 10 Credits
54		=== 11 TODO
55	
56	=== 1 Overview
57	
58	The Makefiles have five parts:
59	
60		Makefile		the top Makefile.
61		.config			the kernel configuration file.
62		arch/$(ARCH)/Makefile	the arch Makefile.
63		scripts/Makefile.*	common rules etc. for all kbuild Makefiles.
64		kbuild Makefiles	there are about 500 of these.
65	
66	The top Makefile reads the .config file, which comes from the kernel
67	configuration process.
68	
69	The top Makefile is responsible for building two major products: vmlinux
70	(the resident kernel image) and modules (any module files).
71	It builds these goals by recursively descending into the subdirectories of
72	the kernel source tree.
73	The list of subdirectories which are visited depends upon the kernel
74	configuration. The top Makefile textually includes an arch Makefile
75	with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
76	architecture-specific information to the top Makefile.
77	
78	Each subdirectory has a kbuild Makefile which carries out the commands
79	passed down from above. The kbuild Makefile uses information from the
80	.config file to construct various file lists used by kbuild to build
81	any built-in or modular targets.
82	
83	scripts/Makefile.* contains all the definitions/rules etc. that
84	are used to build the kernel based on the kbuild makefiles.
85	
86	
87	=== 2 Who does what
88	
89	People have four different relationships with the kernel Makefiles.
90	
91	*Users* are people who build kernels.  These people type commands such as
92	"make menuconfig" or "make".  They usually do not read or edit
93	any kernel Makefiles (or any other source files).
94	
95	*Normal developers* are people who work on features such as device
96	drivers, file systems, and network protocols.  These people need to
97	maintain the kbuild Makefiles for the subsystem they are
98	working on.  In order to do this effectively, they need some overall
99	knowledge about the kernel Makefiles, plus detailed knowledge about the
100	public interface for kbuild.
101	
102	*Arch developers* are people who work on an entire architecture, such
103	as sparc or ia64.  Arch developers need to know about the arch Makefile
104	as well as kbuild Makefiles.
105	
106	*Kbuild developers* are people who work on the kernel build system itself.
107	These people need to know about all aspects of the kernel Makefiles.
108	
109	This document is aimed towards normal developers and arch developers.
110	
111	
112	=== 3 The kbuild files
113	
114	Most Makefiles within the kernel are kbuild Makefiles that use the
115	kbuild infrastructure. This chapter introduces the syntax used in the
116	kbuild makefiles.
117	The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
118	be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
119	file will be used.
120	
121	Section 3.1 "Goal definitions" is a quick intro, further chapters provide
122	more details, with real examples.
123	
124	--- 3.1 Goal definitions
125	
126		Goal definitions are the main part (heart) of the kbuild Makefile.
127		These lines define the files to be built, any special compilation
128		options, and any subdirectories to be entered recursively.
129	
130		The most simple kbuild makefile contains one line:
131	
132		Example:
133			obj-y += foo.o
134	
135		This tells kbuild that there is one object in that directory, named
136		foo.o. foo.o will be built from foo.c or foo.S.
137	
138		If foo.o shall be built as a module, the variable obj-m is used.
139		Therefore the following pattern is often used:
140	
141		Example:
142			obj-$(CONFIG_FOO) += foo.o
143	
144		$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
145		If CONFIG_FOO is neither y nor m, then the file will not be compiled
146		nor linked.
147	
148	--- 3.2 Built-in object goals - obj-y
149	
150		The kbuild Makefile specifies object files for vmlinux
151		in the $(obj-y) lists.  These lists depend on the kernel
152		configuration.
153	
154		Kbuild compiles all the $(obj-y) files.  It then calls
155		"$(LD) -r" to merge these files into one built-in.o file.
156		built-in.o is later linked into vmlinux by the parent Makefile.
157	
158		The order of files in $(obj-y) is significant.  Duplicates in
159		the lists are allowed: the first instance will be linked into
160		built-in.o and succeeding instances will be ignored.
161	
162		Link order is significant, because certain functions
163		(module_init() / __initcall) will be called during boot in the
164		order they appear. So keep in mind that changing the link
165		order may e.g. change the order in which your SCSI
166		controllers are detected, and thus your disks are renumbered.
167	
168		Example:
169			#drivers/isdn/i4l/Makefile
170			# Makefile for the kernel ISDN subsystem and device drivers.
171			# Each configuration option enables a list of files.
172			obj-$(CONFIG_ISDN_I4L)         += isdn.o
173			obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
174	
175	--- 3.3 Loadable module goals - obj-m
176	
177		$(obj-m) specifies object files which are built as loadable
178		kernel modules.
179	
180		A module may be built from one source file or several source
181		files. In the case of one source file, the kbuild makefile
182		simply adds the file to $(obj-m).
183	
184		Example:
185			#drivers/isdn/i4l/Makefile
186			obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
187	
188		Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
189	
190		If a kernel module is built from several source files, you specify
191		that you want to build a module in the same way as above; however,
192		kbuild needs to know which object files you want to build your
193		module from, so you have to tell it by setting a $(<module_name>-y)
194		variable.
195	
196		Example:
197			#drivers/isdn/i4l/Makefile
198			obj-$(CONFIG_ISDN_I4L) += isdn.o
199			isdn-y := isdn_net_lib.o isdn_v110.o isdn_common.o
200	
201		In this example, the module name will be isdn.o. Kbuild will
202		compile the objects listed in $(isdn-y) and then run
203		"$(LD) -r" on the list of these files to generate isdn.o.
204	
205		Due to kbuild recognizing $(<module_name>-y) for composite objects,
206		you can use the value of a CONFIG_ symbol to optionally include an
207		object file as part of a composite object.
208	
209		Example:
210			#fs/ext2/Makefile
211		        obj-$(CONFIG_EXT2_FS) += ext2.o
212			ext2-y := balloc.o dir.o file.o ialloc.o inode.o ioctl.o \
213				  namei.o super.o symlink.o
214		        ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o xattr_user.o \
215							xattr_trusted.o
216	
217		In this example, xattr.o, xattr_user.o and xattr_trusted.o are only
218		part of the composite object ext2.o if $(CONFIG_EXT2_FS_XATTR)
219		evaluates to 'y'.
220	
221		Note: Of course, when you are building objects into the kernel,
222		the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
223		kbuild will build an ext2.o file for you out of the individual
224		parts and then link this into built-in.o, as you would expect.
225	
226	--- 3.4 Objects which export symbols
227	
228		No special notation is required in the makefiles for
229		modules exporting symbols.
230	
231	--- 3.5 Library file goals - lib-y
232	
233		Objects listed with obj-* are used for modules, or
234		combined in a built-in.o for that specific directory.
235		There is also the possibility to list objects that will
236		be included in a library, lib.a.
237		All objects listed with lib-y are combined in a single
238		library for that directory.
239		Objects that are listed in obj-y and additionally listed in
240		lib-y will not be included in the library, since they will
241		be accessible anyway.
242		For consistency, objects listed in lib-m will be included in lib.a.
243	
244		Note that the same kbuild makefile may list files to be built-in
245		and to be part of a library. Therefore the same directory
246		may contain both a built-in.o and a lib.a file.
247	
248		Example:
249			#arch/x86/lib/Makefile
250			lib-y    := delay.o
251	
252		This will create a library lib.a based on delay.o. For kbuild to
253		actually recognize that there is a lib.a being built, the directory
254		shall be listed in libs-y.
255		See also "6.4 List directories to visit when descending".
256	
257		Use of lib-y is normally restricted to lib/ and arch/*/lib.
258	
259	--- 3.6 Descending down in directories
260	
261		A Makefile is only responsible for building objects in its own
262		directory. Files in subdirectories should be taken care of by
263		Makefiles in these subdirs. The build system will automatically
264		invoke make recursively in subdirectories, provided you let it know of
265		them.
266	
267		To do so, obj-y and obj-m are used.
268		ext2 lives in a separate directory, and the Makefile present in fs/
269		tells kbuild to descend down using the following assignment.
270	
271		Example:
272			#fs/Makefile
273			obj-$(CONFIG_EXT2_FS) += ext2/
274	
275		If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
276		the corresponding obj- variable will be set, and kbuild will descend
277		down in the ext2 directory.
278		Kbuild only uses this information to decide that it needs to visit
279		the directory, it is the Makefile in the subdirectory that
280		specifies what is modular and what is built-in.
281	
282		It is good practice to use a CONFIG_ variable when assigning directory
283		names. This allows kbuild to totally skip the directory if the
284		corresponding CONFIG_ option is neither 'y' nor 'm'.
285	
286	--- 3.7 Compilation flags
287	
288	    ccflags-y, asflags-y and ldflags-y
289		These three flags apply only to the kbuild makefile in which they
290		are assigned. They are used for all the normal cc, as and ld
291		invocations happening during a recursive build.
292		Note: Flags with the same behaviour were previously named:
293		EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
294		They are still supported but their usage is deprecated.
295	
296		ccflags-y specifies options for compiling with $(CC).
297	
298		Example:
299			# drivers/acpi/Makefile
300			ccflags-y := -Os
301			ccflags-$(CONFIG_ACPI_DEBUG) += -DACPI_DEBUG_OUTPUT
302	
303		This variable is necessary because the top Makefile owns the
304		variable $(KBUILD_CFLAGS) and uses it for compilation flags for the
305		entire tree.
306	
307		asflags-y specifies options for assembling with $(AS).
308	
309		Example:
310			#arch/sparc/kernel/Makefile
311			asflags-y := -ansi
312	
313		ldflags-y specifies options for linking with $(LD).
314	
315		Example:
316			#arch/cris/boot/compressed/Makefile
317			ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds
318	
319	    subdir-ccflags-y, subdir-asflags-y
320		The two flags listed above are similar to ccflags-y and asflags-y.
321		The difference is that the subdir- variants have effect for the kbuild
322		file where they are present and all subdirectories.
323		Options specified using subdir-* are added to the commandline before
324		the options specified using the non-subdir variants.
325	
326		Example:
327			subdir-ccflags-y := -Werror
328	
329	    CFLAGS_$@, AFLAGS_$@
330	
331		CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
332		kbuild makefile.
333	
334		$(CFLAGS_$@) specifies per-file options for $(CC).  The $@
335		part has a literal value which specifies the file that it is for.
336	
337		Example:
338			# drivers/scsi/Makefile
339			CFLAGS_aha152x.o =   -DAHA152X_STAT -DAUTOCONF
340			CFLAGS_gdth.o    = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
341					     -DGDTH_STATISTICS
342	
343		These two lines specify compilation flags for aha152x.o and gdth.o.
344	
345		$(AFLAGS_$@) is a similar feature for source files in assembly
346		languages.
347	
348		Example:
349			# arch/arm/kernel/Makefile
350			AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
351			AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
352			AFLAGS_iwmmxt.o      := -Wa,-mcpu=iwmmxt
353	
354	
355	--- 3.9 Dependency tracking
356	
357		Kbuild tracks dependencies on the following:
358		1) All prerequisite files (both *.c and *.h)
359		2) CONFIG_ options used in all prerequisite files
360		3) Command-line used to compile target
361	
362		Thus, if you change an option to $(CC) all affected files will
363		be re-compiled.
364	
365	--- 3.10 Special Rules
366	
367		Special rules are used when the kbuild infrastructure does
368		not provide the required support. A typical example is
369		header files generated during the build process.
370		Another example are the architecture-specific Makefiles which
371		need special rules to prepare boot images etc.
372	
373		Special rules are written as normal Make rules.
374		Kbuild is not executing in the directory where the Makefile is
375		located, so all special rules shall provide a relative
376		path to prerequisite files and target files.
377	
378		Two variables are used when defining special rules:
379	
380	    $(src)
381		$(src) is a relative path which points to the directory
382		where the Makefile is located. Always use $(src) when
383		referring to files located in the src tree.
384	
385	    $(obj)
386		$(obj) is a relative path which points to the directory
387		where the target is saved. Always use $(obj) when
388		referring to generated files.
389	
390		Example:
391			#drivers/scsi/Makefile
392			$(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
393				$(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
394	
395		This is a special rule, following the normal syntax
396		required by make.
397		The target file depends on two prerequisite files. References
398		to the target file are prefixed with $(obj), references
399		to prerequisites are referenced with $(src) (because they are not
400		generated files).
401	
402	    $(kecho)
403		echoing information to user in a rule is often a good practice
404		but when execution "make -s" one does not expect to see any output
405		except for warnings/errors.
406		To support this kbuild defines $(kecho) which will echo out the
407		text following $(kecho) to stdout except if "make -s" is used.
408	
409		Example:
410			#arch/blackfin/boot/Makefile
411			$(obj)/vmImage: $(obj)/vmlinux.gz
412				$(call if_changed,uimage)
413				@$(kecho) 'Kernel: $@ is ready'
414	
415	
416	--- 3.11 $(CC) support functions
417	
418		The kernel may be built with several different versions of
419		$(CC), each supporting a unique set of features and options.
420		kbuild provides basic support to check for valid options for $(CC).
421		$(CC) is usually the gcc compiler, but other alternatives are
422		available.
423	
424	    as-option
425		as-option is used to check if $(CC) -- when used to compile
426		assembler (*.S) files -- supports the given option. An optional
427		second option may be specified if the first option is not supported.
428	
429		Example:
430			#arch/sh/Makefile
431			cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
432	
433		In the above example, cflags-y will be assigned the option
434		-Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
435		The second argument is optional, and if supplied will be used
436		if first argument is not supported.
437	
438	    cc-ldoption
439		cc-ldoption is used to check if $(CC) when used to link object files
440		supports the given option.  An optional second option may be
441		specified if first option are not supported.
442	
443		Example:
444			#arch/x86/kernel/Makefile
445			vsyscall-flags += $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
446	
447		In the above example, vsyscall-flags will be assigned the option
448		-Wl$(comma)--hash-style=sysv if it is supported by $(CC).
449		The second argument is optional, and if supplied will be used
450		if first argument is not supported.
451	
452	    as-instr
453		as-instr checks if the assembler reports a specific instruction
454		and then outputs either option1 or option2
455		C escapes are supported in the test instruction
456		Note: as-instr-option uses KBUILD_AFLAGS for $(AS) options
457	
458	    cc-option
459		cc-option is used to check if $(CC) supports a given option, and if
460		not supported to use an optional second option.
461	
462		Example:
463			#arch/x86/Makefile
464			cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
465	
466		In the above example, cflags-y will be assigned the option
467		-march=pentium-mmx if supported by $(CC), otherwise -march=i586.
468		The second argument to cc-option is optional, and if omitted,
469		cflags-y will be assigned no value if first option is not supported.
470		Note: cc-option uses KBUILD_CFLAGS for $(CC) options
471	
472	   cc-option-yn
473		cc-option-yn is used to check if gcc supports a given option
474		and return 'y' if supported, otherwise 'n'.
475	
476		Example:
477			#arch/ppc/Makefile
478			biarch := $(call cc-option-yn, -m32)
479			aflags-$(biarch) += -a32
480			cflags-$(biarch) += -m32
481	
482		In the above example, $(biarch) is set to y if $(CC) supports the -m32
483		option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
484		and $(cflags-y) will be assigned the values -a32 and -m32,
485		respectively.
486		Note: cc-option-yn uses KBUILD_CFLAGS for $(CC) options
487	
488	    cc-option-align
489		gcc versions >= 3.0 changed the type of options used to specify
490		alignment of functions, loops etc. $(cc-option-align), when used
491		as prefix to the align options, will select the right prefix:
492		gcc < 3.00
493			cc-option-align = -malign
494		gcc >= 3.00
495			cc-option-align = -falign
496	
497		Example:
498			KBUILD_CFLAGS += $(cc-option-align)-functions=4
499	
500		In the above example, the option -falign-functions=4 is used for
501		gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
502		Note: cc-option-align uses KBUILD_CFLAGS for $(CC) options
503	
504	    cc-disable-warning
505		cc-disable-warning checks if gcc supports a given warning and returns
506		the commandline switch to disable it. This special function is needed,
507		because gcc 4.4 and later accept any unknown -Wno-* option and only
508		warn about it if there is another warning in the source file.
509	
510		Example:
511			KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
512	
513		In the above example, -Wno-unused-but-set-variable will be added to
514		KBUILD_CFLAGS only if gcc really accepts it.
515	
516	    cc-version
517		cc-version returns a numerical version of the $(CC) compiler version.
518		The format is <major><minor> where both are two digits. So for example
519		gcc 3.41 would return 0341.
520		cc-version is useful when a specific $(CC) version is faulty in one
521		area, for example -mregparm=3 was broken in some gcc versions
522		even though the option was accepted by gcc.
523	
524		Example:
525			#arch/x86/Makefile
526			cflags-y += $(shell \
527			if [ $(cc-version) -ge 0300 ] ; then \
528				echo "-mregparm=3"; fi ;)
529	
530		In the above example, -mregparm=3 is only used for gcc version greater
531		than or equal to gcc 3.0.
532	
533	    cc-ifversion
534		cc-ifversion tests the version of $(CC) and equals the fourth parameter
535		if version expression is true, or the fifth (if given) if the version
536		expression is false.
537	
538		Example:
539			#fs/reiserfs/Makefile
540			ccflags-y := $(call cc-ifversion, -lt, 0402, -O1)
541	
542		In this example, ccflags-y will be assigned the value -O1 if the
543		$(CC) version is less than 4.2.
544		cc-ifversion takes all the shell operators:
545		-eq, -ne, -lt, -le, -gt, and -ge
546		The third parameter may be a text as in this example, but it may also
547		be an expanded variable or a macro.
548	
549	    cc-fullversion
550		cc-fullversion is useful when the exact version of gcc is needed.
551		One typical use-case is when a specific GCC version is broken.
552		cc-fullversion points out a more specific version than cc-version does.
553	
554		Example:
555			#arch/powerpc/Makefile
556			$(Q)if test "$(cc-fullversion)" = "040200" ; then \
557				echo -n '*** GCC-4.2.0 cannot compile the 64-bit powerpc ' ; \
558				false ; \
559			fi
560	
561		In this example for a specific GCC version the build will error out
562		explaining to the user why it stops.
563	
564	    cc-cross-prefix
565		cc-cross-prefix is used to check if there exists a $(CC) in path with
566		one of the listed prefixes. The first prefix where there exist a
567		prefix$(CC) in the PATH is returned - and if no prefix$(CC) is found
568		then nothing is returned.
569		Additional prefixes are separated by a single space in the
570		call of cc-cross-prefix.
571		This functionality is useful for architecture Makefiles that try
572		to set CROSS_COMPILE to well-known values but may have several
573		values to select between.
574		It is recommended only to try to set CROSS_COMPILE if it is a cross
575		build (host arch is different from target arch). And if CROSS_COMPILE
576		is already set then leave it with the old value.
577	
578		Example:
579			#arch/m68k/Makefile
580			ifneq ($(SUBARCH),$(ARCH))
581			        ifeq ($(CROSS_COMPILE),)
582			               CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu-)
583				endif
584			endif
585	
586	--- 3.12 $(LD) support functions
587	
588	    ld-option
589		ld-option is used to check if $(LD) supports the supplied option.
590		ld-option takes two options as arguments.
591		The second argument is an optional option that can be used if the
592		first option is not supported by $(LD).
593	
594		Example:
595			#Makefile
596			LDFLAGS_vmlinux += $(call ld-option, -X)
597	
598	
599	=== 4 Host Program support
600	
601	Kbuild supports building executables on the host for use during the
602	compilation stage.
603	Two steps are required in order to use a host executable.
604	
605	The first step is to tell kbuild that a host program exists. This is
606	done utilising the variable hostprogs-y.
607	
608	The second step is to add an explicit dependency to the executable.
609	This can be done in two ways. Either add the dependency in a rule,
610	or utilise the variable $(always).
611	Both possibilities are described in the following.
612	
613	--- 4.1 Simple Host Program
614	
615		In some cases there is a need to compile and run a program on the
616		computer where the build is running.
617		The following line tells kbuild that the program bin2hex shall be
618		built on the build host.
619	
620		Example:
621			hostprogs-y := bin2hex
622	
623		Kbuild assumes in the above example that bin2hex is made from a single
624		c-source file named bin2hex.c located in the same directory as
625		the Makefile.
626	
627	--- 4.2 Composite Host Programs
628	
629		Host programs can be made up based on composite objects.
630		The syntax used to define composite objects for host programs is
631		similar to the syntax used for kernel objects.
632		$(<executable>-objs) lists all objects used to link the final
633		executable.
634	
635		Example:
636			#scripts/lxdialog/Makefile
637			hostprogs-y   := lxdialog
638			lxdialog-objs := checklist.o lxdialog.o
639	
640		Objects with extension .o are compiled from the corresponding .c
641		files. In the above example, checklist.c is compiled to checklist.o
642		and lxdialog.c is compiled to lxdialog.o.
643		Finally, the two .o files are linked to the executable, lxdialog.
644		Note: The syntax <executable>-y is not permitted for host-programs.
645	
646	--- 4.3 Using C++ for host programs
647	
648		kbuild offers support for host programs written in C++. This was
649		introduced solely to support kconfig, and is not recommended
650		for general use.
651	
652		Example:
653			#scripts/kconfig/Makefile
654			hostprogs-y   := qconf
655			qconf-cxxobjs := qconf.o
656	
657		In the example above the executable is composed of the C++ file
658		qconf.cc - identified by $(qconf-cxxobjs).
659	
660		If qconf is composed of a mixture of .c and .cc files, then an
661		additional line can be used to identify this.
662	
663		Example:
664			#scripts/kconfig/Makefile
665			hostprogs-y   := qconf
666			qconf-cxxobjs := qconf.o
667			qconf-objs    := check.o
668	
669	--- 4.4 Controlling compiler options for host programs
670	
671		When compiling host programs, it is possible to set specific flags.
672		The programs will always be compiled utilising $(HOSTCC) passed
673		the options specified in $(HOSTCFLAGS).
674		To set flags that will take effect for all host programs created
675		in that Makefile, use the variable HOST_EXTRACFLAGS.
676	
677		Example:
678			#scripts/lxdialog/Makefile
679			HOST_EXTRACFLAGS += -I/usr/include/ncurses
680	
681		To set specific flags for a single file the following construction
682		is used:
683	
684		Example:
685			#arch/ppc64/boot/Makefile
686			HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
687	
688		It is also possible to specify additional options to the linker.
689	
690		Example:
691			#scripts/kconfig/Makefile
692			HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
693	
694		When linking qconf, it will be passed the extra option
695		"-L$(QTDIR)/lib".
696	
697	--- 4.5 When host programs are actually built
698	
699		Kbuild will only build host-programs when they are referenced
700		as a prerequisite.
701		This is possible in two ways:
702	
703		(1) List the prerequisite explicitly in a special rule.
704	
705		Example:
706			#drivers/pci/Makefile
707			hostprogs-y := gen-devlist
708			$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
709				( cd $(obj); ./gen-devlist ) < $<
710	
711		The target $(obj)/devlist.h will not be built before
712		$(obj)/gen-devlist is updated. Note that references to
713		the host programs in special rules must be prefixed with $(obj).
714	
715		(2) Use $(always)
716		When there is no suitable special rule, and the host program
717		shall be built when a makefile is entered, the $(always)
718		variable shall be used.
719	
720		Example:
721			#scripts/lxdialog/Makefile
722			hostprogs-y   := lxdialog
723			always        := $(hostprogs-y)
724	
725		This will tell kbuild to build lxdialog even if not referenced in
726		any rule.
727	
728	--- 4.6 Using hostprogs-$(CONFIG_FOO)
729	
730		A typical pattern in a Kbuild file looks like this:
731	
732		Example:
733			#scripts/Makefile
734			hostprogs-$(CONFIG_KALLSYMS) += kallsyms
735	
736		Kbuild knows about both 'y' for built-in and 'm' for module.
737		So if a config symbol evaluates to 'm', kbuild will still build
738		the binary. In other words, Kbuild handles hostprogs-m exactly
739		like hostprogs-y. But only hostprogs-y is recommended to be used
740		when no CONFIG symbols are involved.
741	
742	=== 5 Kbuild clean infrastructure
743	
744	"make clean" deletes most generated files in the obj tree where the kernel
745	is compiled. This includes generated files such as host programs.
746	Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
747	$(extra-y) and $(targets). They are all deleted during "make clean".
748	Files matching the patterns "*.[oas]", "*.ko", plus some additional files
749	generated by kbuild are deleted all over the kernel src tree when
750	"make clean" is executed.
751	
752	Additional files can be specified in kbuild makefiles by use of $(clean-files).
753	
754		Example:
755			#lib/Makefile
756			clean-files := crc32table.h
757	
758	When executing "make clean", the file "crc32table.h" will be deleted.
759	Kbuild will assume files to be in the same relative directory as the
760	Makefile, except if prefixed with $(objtree).
761	
762	To delete a directory hierarchy use:
763	
764		Example:
765			#scripts/package/Makefile
766			clean-dirs := $(objtree)/debian/
767	
768	This will delete the directory debian in the toplevel directory, including all
769	subdirectories.
770	
771	To exclude certain files from make clean, use the $(no-clean-files) variable.
772	This is only a special case used in the top level Kbuild file:
773	
774		Example:
775			#Kbuild
776			no-clean-files := $(bounds-file) $(offsets-file)
777	
778	Usually kbuild descends down in subdirectories due to "obj-* := dir/",
779	but in the architecture makefiles where the kbuild infrastructure
780	is not sufficient this sometimes needs to be explicit.
781	
782		Example:
783			#arch/x86/boot/Makefile
784			subdir- := compressed/
785	
786	The above assignment instructs kbuild to descend down in the
787	directory compressed/ when "make clean" is executed.
788	
789	To support the clean infrastructure in the Makefiles that build the
790	final bootimage there is an optional target named archclean:
791	
792		Example:
793			#arch/x86/Makefile
794			archclean:
795				$(Q)$(MAKE) $(clean)=arch/x86/boot
796	
797	When "make clean" is executed, make will descend down in arch/x86/boot,
798	and clean as usual. The Makefile located in arch/x86/boot/ may use
799	the subdir- trick to descend further down.
800	
801	Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
802	included in the top level makefile, and the kbuild infrastructure
803	is not operational at that point.
804	
805	Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
806	be visited during "make clean".
807	
808	=== 6 Architecture Makefiles
809	
810	The top level Makefile sets up the environment and does the preparation,
811	before starting to descend down in the individual directories.
812	The top level makefile contains the generic part, whereas
813	arch/$(ARCH)/Makefile contains what is required to set up kbuild
814	for said architecture.
815	To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
816	a few targets.
817	
818	When kbuild executes, the following steps are followed (roughly):
819	1) Configuration of the kernel => produce .config
820	2) Store kernel version in include/linux/version.h
821	3) Updating all other prerequisites to the target prepare:
822	   - Additional prerequisites are specified in arch/$(ARCH)/Makefile
823	4) Recursively descend down in all directories listed in
824	   init-* core* drivers-* net-* libs-* and build all targets.
825	   - The values of the above variables are expanded in arch/$(ARCH)/Makefile.
826	5) All object files are then linked and the resulting file vmlinux is
827	   located at the root of the obj tree.
828	   The very first objects linked are listed in head-y, assigned by
829	   arch/$(ARCH)/Makefile.
830	6) Finally, the architecture-specific part does any required post processing
831	   and builds the final bootimage.
832	   - This includes building boot records
833	   - Preparing initrd images and the like
834	
835	
836	--- 6.1 Set variables to tweak the build to the architecture
837	
838	    LDFLAGS		Generic $(LD) options
839	
840		Flags used for all invocations of the linker.
841		Often specifying the emulation is sufficient.
842	
843		Example:
844			#arch/s390/Makefile
845			LDFLAGS         := -m elf_s390
846		Note: ldflags-y can be used to further customise
847		the flags used. See chapter 3.7.
848	
849	    LDFLAGS_MODULE	Options for $(LD) when linking modules
850	
851		LDFLAGS_MODULE is used to set specific flags for $(LD) when
852		linking the .ko files used for modules.
853		Default is "-r", for relocatable output.
854	
855	    LDFLAGS_vmlinux	Options for $(LD) when linking vmlinux
856	
857		LDFLAGS_vmlinux is used to specify additional flags to pass to
858		the linker when linking the final vmlinux image.
859		LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
860	
861		Example:
862			#arch/x86/Makefile
863			LDFLAGS_vmlinux := -e stext
864	
865	    OBJCOPYFLAGS	objcopy flags
866	
867		When $(call if_changed,objcopy) is used to translate a .o file,
868		the flags specified in OBJCOPYFLAGS will be used.
869		$(call if_changed,objcopy) is often used to generate raw binaries on
870		vmlinux.
871	
872		Example:
873			#arch/s390/Makefile
874			OBJCOPYFLAGS := -O binary
875	
876			#arch/s390/boot/Makefile
877			$(obj)/image: vmlinux FORCE
878				$(call if_changed,objcopy)
879	
880		In this example, the binary $(obj)/image is a binary version of
881		vmlinux. The usage of $(call if_changed,xxx) will be described later.
882	
883	    KBUILD_AFLAGS		$(AS) assembler flags
884	
885		Default value - see top level Makefile
886		Append or modify as required per architecture.
887	
888		Example:
889			#arch/sparc64/Makefile
890			KBUILD_AFLAGS += -m64 -mcpu=ultrasparc
891	
892	    KBUILD_CFLAGS		$(CC) compiler flags
893	
894		Default value - see top level Makefile
895		Append or modify as required per architecture.
896	
897		Often, the KBUILD_CFLAGS variable depends on the configuration.
898	
899		Example:
900			#arch/x86/boot/compressed/Makefile
901			cflags-$(CONFIG_X86_32) := -march=i386
902			cflags-$(CONFIG_X86_64) := -mcmodel=small
903			KBUILD_CFLAGS += $(cflags-y)
904	
905		Many arch Makefiles dynamically run the target C compiler to
906		probe supported options:
907	
908			#arch/x86/Makefile
909	
910			...
911			cflags-$(CONFIG_MPENTIUMII)     += $(call cc-option,\
912							-march=pentium2,-march=i686)
913			...
914			# Disable unit-at-a-time mode ...
915			KBUILD_CFLAGS += $(call cc-option,-fno-unit-at-a-time)
916			...
917	
918	
919		The first example utilises the trick that a config option expands
920		to 'y' when selected.
921	
922	    KBUILD_AFLAGS_KERNEL	$(AS) options specific for built-in
923	
924		$(KBUILD_AFLAGS_KERNEL) contains extra C compiler flags used to compile
925		resident kernel code.
926	
927	    KBUILD_AFLAGS_MODULE   Options for $(AS) when building modules
928	
929		$(KBUILD_AFLAGS_MODULE) is used to add arch-specific options that
930		are used for $(AS).
931		From commandline AFLAGS_MODULE shall be used (see kbuild.txt).
932	
933	    KBUILD_CFLAGS_KERNEL	$(CC) options specific for built-in
934	
935		$(KBUILD_CFLAGS_KERNEL) contains extra C compiler flags used to compile
936		resident kernel code.
937	
938	    KBUILD_CFLAGS_MODULE   Options for $(CC) when building modules
939	
940		$(KBUILD_CFLAGS_MODULE) is used to add arch-specific options that
941		are used for $(CC).
942		From commandline CFLAGS_MODULE shall be used (see kbuild.txt).
943	
944	    KBUILD_LDFLAGS_MODULE   Options for $(LD) when linking modules
945	
946		$(KBUILD_LDFLAGS_MODULE) is used to add arch-specific options
947		used when linking modules. This is often a linker script.
948		From commandline LDFLAGS_MODULE shall be used (see kbuild.txt).
949	
950	    KBUILD_ARFLAGS   Options for $(AR) when creating archives
951	
952		$(KBUILD_ARFLAGS) set by the top level Makefile to "D" (deterministic
953		mode) if this option is supported by $(AR).
954	
955	    ARCH_CPPFLAGS, ARCH_AFLAGS, ARCH_CFLAGS   Overrides the kbuild defaults
956	
957		These variables are appended to the KBUILD_CPPFLAGS,
958		KBUILD_AFLAGS, and KBUILD_CFLAGS, respectively, after the
959		top-level Makefile has set any other flags. This provides a
960		means for an architecture to override the defaults.
961	
962	
963	--- 6.2 Add prerequisites to archheaders:
964	
965		The archheaders: rule is used to generate header files that
966		may be installed into user space by "make header_install" or
967		"make headers_install_all".  In order to support
968		"make headers_install_all", this target has to be able to run
969		on an unconfigured tree, or a tree configured for another
970		architecture.
971	
972		It is run before "make archprepare" when run on the
973		architecture itself.
974	
975	
976	--- 6.3 Add prerequisites to archprepare:
977	
978		The archprepare: rule is used to list prerequisites that need to be
979		built before starting to descend down in the subdirectories.
980		This is usually used for header files containing assembler constants.
981	
982			Example:
983			#arch/arm/Makefile
984			archprepare: maketools
985	
986		In this example, the file target maketools will be processed
987		before descending down in the subdirectories.
988		See also chapter XXX-TODO that describe how kbuild supports
989		generating offset header files.
990	
991	
992	--- 6.4 List directories to visit when descending
993	
994		An arch Makefile cooperates with the top Makefile to define variables
995		which specify how to build the vmlinux file.  Note that there is no
996		corresponding arch-specific section for modules; the module-building
997		machinery is all architecture-independent.
998	
999	
1000	    head-y, init-y, core-y, libs-y, drivers-y, net-y
1001	
1002		$(head-y) lists objects to be linked first in vmlinux.
1003		$(libs-y) lists directories where a lib.a archive can be located.
1004		The rest list directories where a built-in.o object file can be
1005		located.
1006	
1007		$(init-y) objects will be located after $(head-y).
1008		Then the rest follows in this order:
1009		$(core-y), $(libs-y), $(drivers-y) and $(net-y).
1010	
1011		The top level Makefile defines values for all generic directories,
1012		and arch/$(ARCH)/Makefile only adds architecture-specific directories.
1013	
1014		Example:
1015			#arch/sparc64/Makefile
1016			core-y += arch/sparc64/kernel/
1017			libs-y += arch/sparc64/prom/ arch/sparc64/lib/
1018			drivers-$(CONFIG_OPROFILE)  += arch/sparc64/oprofile/
1019	
1020	
1021	--- 6.5 Architecture-specific boot images
1022	
1023		An arch Makefile specifies goals that take the vmlinux file, compress
1024		it, wrap it in bootstrapping code, and copy the resulting files
1025		somewhere. This includes various kinds of installation commands.
1026		The actual goals are not standardized across architectures.
1027	
1028		It is common to locate any additional processing in a boot/
1029		directory below arch/$(ARCH)/.
1030	
1031		Kbuild does not provide any smart way to support building a
1032		target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
1033		call make manually to build a target in boot/.
1034	
1035		The recommended approach is to include shortcuts in
1036		arch/$(ARCH)/Makefile, and use the full path when calling down
1037		into the arch/$(ARCH)/boot/Makefile.
1038	
1039		Example:
1040			#arch/x86/Makefile
1041			boot := arch/x86/boot
1042			bzImage: vmlinux
1043				$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
1044	
1045		"$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
1046		make in a subdirectory.
1047	
1048		There are no rules for naming architecture-specific targets,
1049		but executing "make help" will list all relevant targets.
1050		To support this, $(archhelp) must be defined.
1051	
1052		Example:
1053			#arch/x86/Makefile
1054			define archhelp
1055			  echo  '* bzImage      - Image (arch/$(ARCH)/boot/bzImage)'
1056			endif
1057	
1058		When make is executed without arguments, the first goal encountered
1059		will be built. In the top level Makefile the first goal present
1060		is all:.
1061		An architecture shall always, per default, build a bootable image.
1062		In "make help", the default goal is highlighted with a '*'.
1063		Add a new prerequisite to all: to select a default goal different
1064		from vmlinux.
1065	
1066		Example:
1067			#arch/x86/Makefile
1068			all: bzImage
1069	
1070		When "make" is executed without arguments, bzImage will be built.
1071	
1072	--- 6.6 Building non-kbuild targets
1073	
1074	    extra-y
1075	
1076		extra-y specifies additional targets created in the current
1077		directory, in addition to any targets specified by obj-*.
1078	
1079		Listing all targets in extra-y is required for two purposes:
1080		1) Enable kbuild to check changes in command lines
1081		   - When $(call if_changed,xxx) is used
1082		2) kbuild knows what files to delete during "make clean"
1083	
1084		Example:
1085			#arch/x86/kernel/Makefile
1086			extra-y := head.o init_task.o
1087	
1088		In this example, extra-y is used to list object files that
1089		shall be built, but shall not be linked as part of built-in.o.
1090	
1091	
1092	--- 6.7 Commands useful for building a boot image
1093	
1094		Kbuild provides a few macros that are useful when building a
1095		boot image.
1096	
1097	    if_changed
1098	
1099		if_changed is the infrastructure used for the following commands.
1100	
1101		Usage:
1102			target: source(s) FORCE
1103				$(call if_changed,ld/objcopy/gzip/...)
1104	
1105		When the rule is evaluated, it is checked to see if any files
1106		need an update, or the command line has changed since the last
1107		invocation. The latter will force a rebuild if any options
1108		to the executable have changed.
1109		Any target that utilises if_changed must be listed in $(targets),
1110		otherwise the command line check will fail, and the target will
1111		always be built.
1112		Assignments to $(targets) are without $(obj)/ prefix.
1113		if_changed may be used in conjunction with custom commands as
1114		defined in 6.8 "Custom kbuild commands".
1115	
1116		Note: It is a typical mistake to forget the FORCE prerequisite.
1117		Another common pitfall is that whitespace is sometimes
1118		significant; for instance, the below will fail (note the extra space
1119		after the comma):
1120			target: source(s) FORCE
1121		#WRONG!#	$(call if_changed, ld/objcopy/gzip/...)
1122	
1123	    ld
1124		Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
1125	
1126	    objcopy
1127		Copy binary. Uses OBJCOPYFLAGS usually specified in
1128		arch/$(ARCH)/Makefile.
1129		OBJCOPYFLAGS_$@ may be used to set additional options.
1130	
1131	    gzip
1132		Compress target. Use maximum compression to compress target.
1133	
1134		Example:
1135			#arch/x86/boot/Makefile
1136			LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
1137			LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext
1138	
1139			targets += setup setup.o bootsect bootsect.o
1140			$(obj)/setup $(obj)/bootsect: %: %.o FORCE
1141				$(call if_changed,ld)
1142	
1143		In this example, there are two possible targets, requiring different
1144		options to the linker. The linker options are specified using the
1145		LDFLAGS_$@ syntax - one for each potential target.
1146		$(targets) are assigned all potential targets, by which kbuild knows
1147		the targets and will:
1148			1) check for commandline changes
1149			2) delete target during make clean
1150	
1151		The ": %: %.o" part of the prerequisite is a shorthand that
1152		frees us from listing the setup.o and bootsect.o files.
1153		Note: It is a common mistake to forget the "targets :=" assignment,
1154		      resulting in the target file being recompiled for no
1155		      obvious reason.
1156	
1157	    dtc
1158		Create flattened device tree blob object suitable for linking
1159		into vmlinux. Device tree blobs linked into vmlinux are placed
1160		in an init section in the image. Platform code *must* copy the
1161		blob to non-init memory prior to calling unflatten_device_tree().
1162	
1163		To use this command, simply add *.dtb into obj-y or targets, or make
1164		some other target depend on %.dtb
1165	
1166		A central rule exists to create $(obj)/%.dtb from $(src)/%.dts;
1167		architecture Makefiles do no need to explicitly write out that rule.
1168	
1169		Example:
1170			targets += $(dtb-y)
1171			clean-files += *.dtb
1172			DTC_FLAGS ?= -p 1024
1173	
1174	--- 6.8 Custom kbuild commands
1175	
1176		When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
1177		of a command is normally displayed.
1178		To enable this behaviour for custom commands kbuild requires
1179		two variables to be set:
1180		quiet_cmd_<command>	- what shall be echoed
1181		      cmd_<command>	- the command to execute
1182	
1183		Example:
1184			#
1185			quiet_cmd_image = BUILD   $@
1186			      cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
1187			                                     $(obj)/vmlinux.bin > $@
1188	
1189			targets += bzImage
1190			$(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
1191				$(call if_changed,image)
1192				@echo 'Kernel: $@ is ready'
1193	
1194		When updating the $(obj)/bzImage target, the line
1195	
1196		BUILD    arch/x86/boot/bzImage
1197	
1198		will be displayed with "make KBUILD_VERBOSE=0".
1199	
1200	
1201	--- 6.9 Preprocessing linker scripts
1202	
1203		When the vmlinux image is built, the linker script
1204		arch/$(ARCH)/kernel/vmlinux.lds is used.
1205		The script is a preprocessed variant of the file vmlinux.lds.S
1206		located in the same directory.
1207		kbuild knows .lds files and includes a rule *lds.S -> *lds.
1208	
1209		Example:
1210			#arch/x86/kernel/Makefile
1211			always := vmlinux.lds
1212	
1213			#Makefile
1214			export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
1215	
1216		The assignment to $(always) is used to tell kbuild to build the
1217		target vmlinux.lds.
1218		The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
1219		specified options when building the target vmlinux.lds.
1220	
1221		When building the *.lds target, kbuild uses the variables:
1222		KBUILD_CPPFLAGS	: Set in top-level Makefile
1223		cppflags-y	: May be set in the kbuild makefile
1224		CPPFLAGS_$(@F)  : Target-specific flags.
1225		                  Note that the full filename is used in this
1226		                  assignment.
1227	
1228		The kbuild infrastructure for *lds files is used in several
1229		architecture-specific files.
1230	
1231	--- 6.10 Generic header files
1232	
1233		The directory include/asm-generic contains the header files
1234		that may be shared between individual architectures.
1235		The recommended approach how to use a generic header file is
1236		to list the file in the Kbuild file.
1237		See "7.4 generic-y" for further info on syntax etc.
1238	
1239	=== 7 Kbuild syntax for exported headers
1240	
1241	The kernel includes a set of headers that is exported to userspace.
1242	Many headers can be exported as-is but other headers require a
1243	minimal pre-processing before they are ready for user-space.
1244	The pre-processing does:
1245	- drop kernel-specific annotations
1246	- drop include of compiler.h
1247	- drop all sections that are kernel internal (guarded by ifdef __KERNEL__)
1248	
1249	Each relevant directory contains a file name "Kbuild" which specifies the
1250	headers to be exported.
1251	See subsequent chapter for the syntax of the Kbuild file.
1252	
1253		--- 7.1 header-y
1254	
1255		header-y specifies header files to be exported.
1256	
1257			Example:
1258				#include/linux/Kbuild
1259				header-y += usb/
1260				header-y += aio_abi.h
1261	
1262		The convention is to list one file per line and
1263		preferably in alphabetic order.
1264	
1265		header-y also specifies which subdirectories to visit.
1266		A subdirectory is identified by a trailing '/' which
1267		can be seen in the example above for the usb subdirectory.
1268	
1269		Subdirectories are visited before their parent directories.
1270	
1271		--- 7.2 genhdr-y
1272	
1273		genhdr-y specifies generated files to be exported.
1274		Generated files are special as they need to be looked
1275		up in another directory when doing 'make O=...' builds.
1276	
1277			Example:
1278				#include/linux/Kbuild
1279				genhdr-y += version.h
1280	
1281		--- 7.3 destination-y
1282	
1283		When an architecture has a set of exported headers that needs to be
1284		exported to a different directory destination-y is used.
1285		destination-y specifies the destination directory for all exported
1286		headers in the file where it is present.
1287	
1288			Example:
1289				#arch/xtensa/platforms/s6105/include/platform/Kbuild
1290				destination-y := include/linux
1291	
1292		In the example above all exported headers in the Kbuild file
1293		will be located in the directory "include/linux" when exported.
1294	
1295		--- 7.4 generic-y
1296	
1297		If an architecture uses a verbatim copy of a header from
1298		include/asm-generic then this is listed in the file
1299		arch/$(ARCH)/include/asm/Kbuild like this:
1300	
1301			Example:
1302				#arch/x86/include/asm/Kbuild
1303				generic-y += termios.h
1304				generic-y += rtc.h
1305	
1306		During the prepare phase of the build a wrapper include
1307		file is generated in the directory:
1308	
1309			arch/$(ARCH)/include/generated/asm
1310	
1311		When a header is exported where the architecture uses
1312		the generic header a similar wrapper is generated as part
1313		of the set of exported headers in the directory:
1314	
1315			usr/include/asm
1316	
1317		The generated wrapper will in both cases look like the following:
1318	
1319			Example: termios.h
1320				#include <asm-generic/termios.h>
1321	
1322	=== 8 Kbuild Variables
1323	
1324	The top Makefile exports the following variables:
1325	
1326	    VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
1327	
1328		These variables define the current kernel version.  A few arch
1329		Makefiles actually use these values directly; they should use
1330		$(KERNELRELEASE) instead.
1331	
1332		$(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
1333		three-part version number, such as "2", "4", and "0".  These three
1334		values are always numeric.
1335	
1336		$(EXTRAVERSION) defines an even tinier sublevel for pre-patches
1337		or additional patches.	It is usually some non-numeric string
1338		such as "-pre4", and is often blank.
1339	
1340	    KERNELRELEASE
1341	
1342		$(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
1343		for constructing installation directory names or showing in
1344		version strings.  Some arch Makefiles use it for this purpose.
1345	
1346	    ARCH
1347	
1348		This variable defines the target architecture, such as "i386",
1349		"arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
1350		determine which files to compile.
1351	
1352		By default, the top Makefile sets $(ARCH) to be the same as the
1353		host system architecture.  For a cross build, a user may
1354		override the value of $(ARCH) on the command line:
1355	
1356		    make ARCH=m68k ...
1357	
1358	
1359	    INSTALL_PATH
1360	
1361		This variable defines a place for the arch Makefiles to install
1362		the resident kernel image and System.map file.
1363		Use this for architecture-specific install targets.
1364	
1365	    INSTALL_MOD_PATH, MODLIB
1366	
1367		$(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
1368		installation.  This variable is not defined in the Makefile but
1369		may be passed in by the user if desired.
1370	
1371		$(MODLIB) specifies the directory for module installation.
1372		The top Makefile defines $(MODLIB) to
1373		$(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE).  The user may
1374		override this value on the command line if desired.
1375	
1376	    INSTALL_MOD_STRIP
1377	
1378		If this variable is specified, it will cause modules to be stripped
1379		after they are installed.  If INSTALL_MOD_STRIP is '1', then the
1380		default option --strip-debug will be used.  Otherwise, the
1381		INSTALL_MOD_STRIP value will be used as the option(s) to the strip
1382		command.
1383	
1384	
1385	=== 9 Makefile language
1386	
1387	The kernel Makefiles are designed to be run with GNU Make.  The Makefiles
1388	use only the documented features of GNU Make, but they do use many
1389	GNU extensions.
1390	
1391	GNU Make supports elementary list-processing functions.  The kernel
1392	Makefiles use a novel style of list building and manipulation with few
1393	"if" statements.
1394	
1395	GNU Make has two assignment operators, ":=" and "=".  ":=" performs
1396	immediate evaluation of the right-hand side and stores an actual string
1397	into the left-hand side.  "=" is like a formula definition; it stores the
1398	right-hand side in an unevaluated form and then evaluates this form each
1399	time the left-hand side is used.
1400	
1401	There are some cases where "=" is appropriate.  Usually, though, ":="
1402	is the right choice.
1403	
1404	=== 10 Credits
1405	
1406	Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
1407	Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
1408	Updates by Sam Ravnborg <sam@ravnborg.org>
1409	Language QA by Jan Engelhardt <jengelh@gmx.de>
1410	
1411	=== 11 TODO
1412	
1413	- Describe how kbuild supports shipped files with _shipped.
1414	- Generating offset header files.
1415	- Add more variables to section 7?
1416	
1417	
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