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Based on kernel version 3.13. Page generated on 2014-01-20 22:04 EST.

1	Overview of Linux kernel SPI support
2	====================================
3	
4	02-Feb-2012
5	
6	What is SPI?
7	------------
8	The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
9	link used to connect microcontrollers to sensors, memory, and peripherals.
10	It's a simple "de facto" standard, not complicated enough to acquire a
11	standardization body.  SPI uses a master/slave configuration.
12	
13	The three signal wires hold a clock (SCK, often on the order of 10 MHz),
14	and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
15	Slave Out" (MISO) signals.  (Other names are also used.)  There are four
16	clocking modes through which data is exchanged; mode-0 and mode-3 are most
17	commonly used.  Each clock cycle shifts data out and data in; the clock
18	doesn't cycle except when there is a data bit to shift.  Not all data bits
19	are used though; not every protocol uses those full duplex capabilities.
20	
21	SPI masters use a fourth "chip select" line to activate a given SPI slave
22	device, so those three signal wires may be connected to several chips
23	in parallel.  All SPI slaves support chipselects; they are usually active
24	low signals, labeled nCSx for slave 'x' (e.g. nCS0).  Some devices have
25	other signals, often including an interrupt to the master.
26	
27	Unlike serial busses like USB or SMBus, even low level protocols for
28	SPI slave functions are usually not interoperable between vendors
29	(except for commodities like SPI memory chips).
30	
31	  - SPI may be used for request/response style device protocols, as with
32	    touchscreen sensors and memory chips.
33	
34	  - It may also be used to stream data in either direction (half duplex),
35	    or both of them at the same time (full duplex).
36	
37	  - Some devices may use eight bit words.  Others may different word
38	    lengths, such as streams of 12-bit or 20-bit digital samples.
39	
40	  - Words are usually sent with their most significant bit (MSB) first,
41	    but sometimes the least significant bit (LSB) goes first instead.
42	
43	  - Sometimes SPI is used to daisy-chain devices, like shift registers.
44	
45	In the same way, SPI slaves will only rarely support any kind of automatic
46	discovery/enumeration protocol.  The tree of slave devices accessible from
47	a given SPI master will normally be set up manually, with configuration
48	tables.
49	
50	SPI is only one of the names used by such four-wire protocols, and
51	most controllers have no problem handling "MicroWire" (think of it as
52	half-duplex SPI, for request/response protocols), SSP ("Synchronous
53	Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
54	related protocols.
55	
56	Some chips eliminate a signal line by combining MOSI and MISO, and
57	limiting themselves to half-duplex at the hardware level.  In fact
58	some SPI chips have this signal mode as a strapping option.  These
59	can be accessed using the same programming interface as SPI, but of
60	course they won't handle full duplex transfers.  You may find such
61	chips described as using "three wire" signaling: SCK, data, nCSx.
62	(That data line is sometimes called MOMI or SISO.)
63	
64	Microcontrollers often support both master and slave sides of the SPI
65	protocol.  This document (and Linux) currently only supports the master
66	side of SPI interactions.
67	
68	
69	Who uses it?  On what kinds of systems?
70	---------------------------------------
71	Linux developers using SPI are probably writing device drivers for embedded
72	systems boards.  SPI is used to control external chips, and it is also a
73	protocol supported by every MMC or SD memory card.  (The older "DataFlash"
74	cards, predating MMC cards but using the same connectors and card shape,
75	support only SPI.)  Some PC hardware uses SPI flash for BIOS code.
76	
77	SPI slave chips range from digital/analog converters used for analog
78	sensors and codecs, to memory, to peripherals like USB controllers
79	or Ethernet adapters; and more.
80	
81	Most systems using SPI will integrate a few devices on a mainboard.
82	Some provide SPI links on expansion connectors; in cases where no
83	dedicated SPI controller exists, GPIO pins can be used to create a
84	low speed "bitbanging" adapter.  Very few systems will "hotplug" an SPI
85	controller; the reasons to use SPI focus on low cost and simple operation,
86	and if dynamic reconfiguration is important, USB will often be a more
87	appropriate low-pincount peripheral bus.
88	
89	Many microcontrollers that can run Linux integrate one or more I/O
90	interfaces with SPI modes.  Given SPI support, they could use MMC or SD
91	cards without needing a special purpose MMC/SD/SDIO controller.
92	
93	
94	I'm confused.  What are these four SPI "clock modes"?
95	-----------------------------------------------------
96	It's easy to be confused here, and the vendor documentation you'll
97	find isn't necessarily helpful.  The four modes combine two mode bits:
98	
99	 - CPOL indicates the initial clock polarity.  CPOL=0 means the
100	   clock starts low, so the first (leading) edge is rising, and
101	   the second (trailing) edge is falling.  CPOL=1 means the clock
102	   starts high, so the first (leading) edge is falling.
103	
104	 - CPHA indicates the clock phase used to sample data; CPHA=0 says
105	   sample on the leading edge, CPHA=1 means the trailing edge.
106	
107	   Since the signal needs to stablize before it's sampled, CPHA=0
108	   implies that its data is written half a clock before the first
109	   clock edge.  The chipselect may have made it become available.
110	
111	Chip specs won't always say "uses SPI mode X" in as many words,
112	but their timing diagrams will make the CPOL and CPHA modes clear.
113	
114	In the SPI mode number, CPOL is the high order bit and CPHA is the
115	low order bit.  So when a chip's timing diagram shows the clock
116	starting low (CPOL=0) and data stabilized for sampling during the
117	trailing clock edge (CPHA=1), that's SPI mode 1.
118	
119	Note that the clock mode is relevant as soon as the chipselect goes
120	active.  So the master must set the clock to inactive before selecting
121	a slave, and the slave can tell the chosen polarity by sampling the
122	clock level when its select line goes active.  That's why many devices
123	support for example both modes 0 and 3:  they don't care about polarity,
124	and alway clock data in/out on rising clock edges.
125	
126	
127	How do these driver programming interfaces work?
128	------------------------------------------------
129	The <linux/spi/spi.h> header file includes kerneldoc, as does the
130	main source code, and you should certainly read that chapter of the
131	kernel API document.  This is just an overview, so you get the big
132	picture before those details.
133	
134	SPI requests always go into I/O queues.  Requests for a given SPI device
135	are always executed in FIFO order, and complete asynchronously through
136	completion callbacks.  There are also some simple synchronous wrappers
137	for those calls, including ones for common transaction types like writing
138	a command and then reading its response.
139	
140	There are two types of SPI driver, here called:
141	
142	  Controller drivers ... controllers may be built in to System-On-Chip
143		processors, and often support both Master and Slave roles.
144		These drivers touch hardware registers and may use DMA.
145		Or they can be PIO bitbangers, needing just GPIO pins.
146	
147	  Protocol drivers ... these pass messages through the controller
148		driver to communicate with a Slave or Master device on the
149		other side of an SPI link.
150	
151	So for example one protocol driver might talk to the MTD layer to export
152	data to filesystems stored on SPI flash like DataFlash; and others might
153	control audio interfaces, present touchscreen sensors as input interfaces,
154	or monitor temperature and voltage levels during industrial processing.
155	And those might all be sharing the same controller driver.
156	
157	A "struct spi_device" encapsulates the master-side interface between
158	those two types of driver.  At this writing, Linux has no slave side
159	programming interface.
160	
161	There is a minimal core of SPI programming interfaces, focussing on
162	using the driver model to connect controller and protocol drivers using
163	device tables provided by board specific initialization code.  SPI
164	shows up in sysfs in several locations:
165	
166	   /sys/devices/.../CTLR ... physical node for a given SPI controller
167	
168	   /sys/devices/.../CTLR/spiB.C ... spi_device on bus "B",
169		chipselect C, accessed through CTLR.
170	
171	   /sys/bus/spi/devices/spiB.C ... symlink to that physical
172	   	.../CTLR/spiB.C device
173	
174	   /sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
175		that should be used with this device (for hotplug/coldplug)
176	
177	   /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices
178	
179	   /sys/class/spi_master/spiB ... symlink (or actual device node) to
180		a logical node which could hold class related state for the
181		controller managing bus "B".  All spiB.* devices share one
182		physical SPI bus segment, with SCLK, MOSI, and MISO.
183	
184	Note that the actual location of the controller's class state depends
185	on whether you enabled CONFIG_SYSFS_DEPRECATED or not.  At this time,
186	the only class-specific state is the bus number ("B" in "spiB"), so
187	those /sys/class entries are only useful to quickly identify busses.
188	
189	
190	How does board-specific init code declare SPI devices?
191	------------------------------------------------------
192	Linux needs several kinds of information to properly configure SPI devices.
193	That information is normally provided by board-specific code, even for
194	chips that do support some of automated discovery/enumeration.
195	
196	DECLARE CONTROLLERS
197	
198	The first kind of information is a list of what SPI controllers exist.
199	For System-on-Chip (SOC) based boards, these will usually be platform
200	devices, and the controller may need some platform_data in order to
201	operate properly.  The "struct platform_device" will include resources
202	like the physical address of the controller's first register and its IRQ.
203	
204	Platforms will often abstract the "register SPI controller" operation,
205	maybe coupling it with code to initialize pin configurations, so that
206	the arch/.../mach-*/board-*.c files for several boards can all share the
207	same basic controller setup code.  This is because most SOCs have several
208	SPI-capable controllers, and only the ones actually usable on a given
209	board should normally be set up and registered.
210	
211	So for example arch/.../mach-*/board-*.c files might have code like:
212	
213		#include <mach/spi.h>	/* for mysoc_spi_data */
214	
215		/* if your mach-* infrastructure doesn't support kernels that can
216		 * run on multiple boards, pdata wouldn't benefit from "__init".
217		 */
218		static struct mysoc_spi_data pdata __initdata = { ... };
219	
220		static __init board_init(void)
221		{
222			...
223			/* this board only uses SPI controller #2 */
224			mysoc_register_spi(2, &pdata);
225			...
226		}
227	
228	And SOC-specific utility code might look something like:
229	
230		#include <mach/spi.h>
231	
232		static struct platform_device spi2 = { ... };
233	
234		void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata)
235		{
236			struct mysoc_spi_data *pdata2;
237	
238			pdata2 = kmalloc(sizeof *pdata2, GFP_KERNEL);
239			*pdata2 = pdata;
240			...
241			if (n == 2) {
242				spi2->dev.platform_data = pdata2;
243				register_platform_device(&spi2);
244	
245				/* also: set up pin modes so the spi2 signals are
246				 * visible on the relevant pins ... bootloaders on
247				 * production boards may already have done this, but
248				 * developer boards will often need Linux to do it.
249				 */
250			}
251			...
252		}
253	
254	Notice how the platform_data for boards may be different, even if the
255	same SOC controller is used.  For example, on one board SPI might use
256	an external clock, where another derives the SPI clock from current
257	settings of some master clock.
258	
259	
260	DECLARE SLAVE DEVICES
261	
262	The second kind of information is a list of what SPI slave devices exist
263	on the target board, often with some board-specific data needed for the
264	driver to work correctly.
265	
266	Normally your arch/.../mach-*/board-*.c files would provide a small table
267	listing the SPI devices on each board.  (This would typically be only a
268	small handful.)  That might look like:
269	
270		static struct ads7846_platform_data ads_info = {
271			.vref_delay_usecs	= 100,
272			.x_plate_ohms		= 580,
273			.y_plate_ohms		= 410,
274		};
275	
276		static struct spi_board_info spi_board_info[] __initdata = {
277		{
278			.modalias	= "ads7846",
279			.platform_data	= &ads_info,
280			.mode		= SPI_MODE_0,
281			.irq		= GPIO_IRQ(31),
282			.max_speed_hz	= 120000 /* max sample rate at 3V */ * 16,
283			.bus_num	= 1,
284			.chip_select	= 0,
285		},
286		};
287	
288	Again, notice how board-specific information is provided; each chip may need
289	several types.  This example shows generic constraints like the fastest SPI
290	clock to allow (a function of board voltage in this case) or how an IRQ pin
291	is wired, plus chip-specific constraints like an important delay that's
292	changed by the capacitance at one pin.
293	
294	(There's also "controller_data", information that may be useful to the
295	controller driver.  An example would be peripheral-specific DMA tuning
296	data or chipselect callbacks.  This is stored in spi_device later.)
297	
298	The board_info should provide enough information to let the system work
299	without the chip's driver being loaded.  The most troublesome aspect of
300	that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since
301	sharing a bus with a device that interprets chipselect "backwards" is
302	not possible until the infrastructure knows how to deselect it.
303	
304	Then your board initialization code would register that table with the SPI
305	infrastructure, so that it's available later when the SPI master controller
306	driver is registered:
307	
308		spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
309	
310	Like with other static board-specific setup, you won't unregister those.
311	
312	The widely used "card" style computers bundle memory, cpu, and little else
313	onto a card that's maybe just thirty square centimeters.  On such systems,
314	your arch/.../mach-.../board-*.c file would primarily provide information
315	about the devices on the mainboard into which such a card is plugged.  That
316	certainly includes SPI devices hooked up through the card connectors!
317	
318	
319	NON-STATIC CONFIGURATIONS
320	
321	Developer boards often play by different rules than product boards, and one
322	example is the potential need to hotplug SPI devices and/or controllers.
323	
324	For those cases you might need to use spi_busnum_to_master() to look
325	up the spi bus master, and will likely need spi_new_device() to provide the
326	board info based on the board that was hotplugged.  Of course, you'd later
327	call at least spi_unregister_device() when that board is removed.
328	
329	When Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those
330	configurations will also be dynamic.  Fortunately, such devices all support
331	basic device identification probes, so they should hotplug normally.
332	
333	
334	How do I write an "SPI Protocol Driver"?
335	----------------------------------------
336	Most SPI drivers are currently kernel drivers, but there's also support
337	for userspace drivers.  Here we talk only about kernel drivers.
338	
339	SPI protocol drivers somewhat resemble platform device drivers:
340	
341		static struct spi_driver CHIP_driver = {
342			.driver = {
343				.name		= "CHIP",
344				.owner		= THIS_MODULE,
345			},
346	
347			.probe		= CHIP_probe,
348			.remove		= CHIP_remove,
349			.suspend	= CHIP_suspend,
350			.resume		= CHIP_resume,
351		};
352	
353	The driver core will automatically attempt to bind this driver to any SPI
354	device whose board_info gave a modalias of "CHIP".  Your probe() code
355	might look like this unless you're creating a device which is managing
356	a bus (appearing under /sys/class/spi_master).
357	
358		static int CHIP_probe(struct spi_device *spi)
359		{
360			struct CHIP			*chip;
361			struct CHIP_platform_data	*pdata;
362	
363			/* assuming the driver requires board-specific data: */
364			pdata = &spi->dev.platform_data;
365			if (!pdata)
366				return -ENODEV;
367	
368			/* get memory for driver's per-chip state */
369			chip = kzalloc(sizeof *chip, GFP_KERNEL);
370			if (!chip)
371				return -ENOMEM;
372			spi_set_drvdata(spi, chip);
373	
374			... etc
375			return 0;
376		}
377	
378	As soon as it enters probe(), the driver may issue I/O requests to
379	the SPI device using "struct spi_message".  When remove() returns,
380	or after probe() fails, the driver guarantees that it won't submit
381	any more such messages.
382	
383	  - An spi_message is a sequence of protocol operations, executed
384	    as one atomic sequence.  SPI driver controls include:
385	
386	      + when bidirectional reads and writes start ... by how its
387	        sequence of spi_transfer requests is arranged;
388	
389	      + which I/O buffers are used ... each spi_transfer wraps a
390	        buffer for each transfer direction, supporting full duplex
391	        (two pointers, maybe the same one in both cases) and half
392	        duplex (one pointer is NULL) transfers;
393	
394	      + optionally defining short delays after transfers ... using
395	        the spi_transfer.delay_usecs setting (this delay can be the
396	        only protocol effect, if the buffer length is zero);
397	
398	      + whether the chipselect becomes inactive after a transfer and
399	        any delay ... by using the spi_transfer.cs_change flag;
400	
401	      + hinting whether the next message is likely to go to this same
402	        device ... using the spi_transfer.cs_change flag on the last
403		transfer in that atomic group, and potentially saving costs
404		for chip deselect and select operations.
405	
406	  - Follow standard kernel rules, and provide DMA-safe buffers in
407	    your messages.  That way controller drivers using DMA aren't forced
408	    to make extra copies unless the hardware requires it (e.g. working
409	    around hardware errata that force the use of bounce buffering).
410	
411	    If standard dma_map_single() handling of these buffers is inappropriate,
412	    you can use spi_message.is_dma_mapped to tell the controller driver
413	    that you've already provided the relevant DMA addresses.
414	
415	  - The basic I/O primitive is spi_async().  Async requests may be
416	    issued in any context (irq handler, task, etc) and completion
417	    is reported using a callback provided with the message.
418	    After any detected error, the chip is deselected and processing
419	    of that spi_message is aborted.
420	
421	  - There are also synchronous wrappers like spi_sync(), and wrappers
422	    like spi_read(), spi_write(), and spi_write_then_read().  These
423	    may be issued only in contexts that may sleep, and they're all
424	    clean (and small, and "optional") layers over spi_async().
425	
426	  - The spi_write_then_read() call, and convenience wrappers around
427	    it, should only be used with small amounts of data where the
428	    cost of an extra copy may be ignored.  It's designed to support
429	    common RPC-style requests, such as writing an eight bit command
430	    and reading a sixteen bit response -- spi_w8r16() being one its
431	    wrappers, doing exactly that.
432	
433	Some drivers may need to modify spi_device characteristics like the
434	transfer mode, wordsize, or clock rate.  This is done with spi_setup(),
435	which would normally be called from probe() before the first I/O is
436	done to the device.  However, that can also be called at any time
437	that no message is pending for that device.
438	
439	While "spi_device" would be the bottom boundary of the driver, the
440	upper boundaries might include sysfs (especially for sensor readings),
441	the input layer, ALSA, networking, MTD, the character device framework,
442	or other Linux subsystems.
443	
444	Note that there are two types of memory your driver must manage as part
445	of interacting with SPI devices.
446	
447	  - I/O buffers use the usual Linux rules, and must be DMA-safe.
448	    You'd normally allocate them from the heap or free page pool.
449	    Don't use the stack, or anything that's declared "static".
450	
451	  - The spi_message and spi_transfer metadata used to glue those
452	    I/O buffers into a group of protocol transactions.  These can
453	    be allocated anywhere it's convenient, including as part of
454	    other allocate-once driver data structures.  Zero-init these.
455	
456	If you like, spi_message_alloc() and spi_message_free() convenience
457	routines are available to allocate and zero-initialize an spi_message
458	with several transfers.
459	
460	
461	How do I write an "SPI Master Controller Driver"?
462	-------------------------------------------------
463	An SPI controller will probably be registered on the platform_bus; write
464	a driver to bind to the device, whichever bus is involved.
465	
466	The main task of this type of driver is to provide an "spi_master".
467	Use spi_alloc_master() to allocate the master, and spi_master_get_devdata()
468	to get the driver-private data allocated for that device.
469	
470		struct spi_master	*master;
471		struct CONTROLLER	*c;
472	
473		master = spi_alloc_master(dev, sizeof *c);
474		if (!master)
475			return -ENODEV;
476	
477		c = spi_master_get_devdata(master);
478	
479	The driver will initialize the fields of that spi_master, including the
480	bus number (maybe the same as the platform device ID) and three methods
481	used to interact with the SPI core and SPI protocol drivers.  It will
482	also initialize its own internal state.  (See below about bus numbering
483	and those methods.)
484	
485	After you initialize the spi_master, then use spi_register_master() to
486	publish it to the rest of the system. At that time, device nodes for the
487	controller and any predeclared spi devices will be made available, and
488	the driver model core will take care of binding them to drivers.
489	
490	If you need to remove your SPI controller driver, spi_unregister_master()
491	will reverse the effect of spi_register_master().
492	
493	
494	BUS NUMBERING
495	
496	Bus numbering is important, since that's how Linux identifies a given
497	SPI bus (shared SCK, MOSI, MISO).  Valid bus numbers start at zero.  On
498	SOC systems, the bus numbers should match the numbers defined by the chip
499	manufacturer.  For example, hardware controller SPI2 would be bus number 2,
500	and spi_board_info for devices connected to it would use that number.
501	
502	If you don't have such hardware-assigned bus number, and for some reason
503	you can't just assign them, then provide a negative bus number.  That will
504	then be replaced by a dynamically assigned number. You'd then need to treat
505	this as a non-static configuration (see above).
506	
507	
508	SPI MASTER METHODS
509	
510	    master->setup(struct spi_device *spi)
511		This sets up the device clock rate, SPI mode, and word sizes.
512		Drivers may change the defaults provided by board_info, and then
513		call spi_setup(spi) to invoke this routine.  It may sleep.
514	
515		Unless each SPI slave has its own configuration registers, don't
516		change them right away ... otherwise drivers could corrupt I/O
517		that's in progress for other SPI devices.
518	
519			** BUG ALERT:  for some reason the first version of
520			** many spi_master drivers seems to get this wrong.
521			** When you code setup(), ASSUME that the controller
522			** is actively processing transfers for another device.
523	
524	    master->cleanup(struct spi_device *spi)
525		Your controller driver may use spi_device.controller_state to hold
526		state it dynamically associates with that device.  If you do that,
527		be sure to provide the cleanup() method to free that state.
528	
529	    master->prepare_transfer_hardware(struct spi_master *master)
530		This will be called by the queue mechanism to signal to the driver
531		that a message is coming in soon, so the subsystem requests the
532		driver to prepare the transfer hardware by issuing this call.
533		This may sleep.
534	
535	    master->unprepare_transfer_hardware(struct spi_master *master)
536		This will be called by the queue mechanism to signal to the driver
537		that there are no more messages pending in the queue and it may
538		relax the hardware (e.g. by power management calls). This may sleep.
539	
540	    master->transfer_one_message(struct spi_master *master,
541					 struct spi_message *mesg)
542		The subsystem calls the driver to transfer a single message while
543		queuing transfers that arrive in the meantime. When the driver is
544		finished with this message, it must call
545		spi_finalize_current_message() so the subsystem can issue the next
546		transfer. This may sleep.
547	
548	    DEPRECATED METHODS
549	
550	    master->transfer(struct spi_device *spi, struct spi_message *message)
551		This must not sleep. Its responsibility is arrange that the
552		transfer happens and its complete() callback is issued. The two
553		will normally happen later, after other transfers complete, and
554		if the controller is idle it will need to be kickstarted. This
555		method is not used on queued controllers and must be NULL if
556		transfer_one_message() and (un)prepare_transfer_hardware() are
557		implemented.
558	
559	
560	SPI MESSAGE QUEUE
561	
562	If you are happy with the standard queueing mechanism provided by the
563	SPI subsystem, just implement the queued methods specified above. Using
564	the message queue has the upside of centralizing a lot of code and
565	providing pure process-context execution of methods. The message queue
566	can also be elevated to realtime priority on high-priority SPI traffic.
567	
568	Unless the queueing mechanism in the SPI subsystem is selected, the bulk
569	of the driver will be managing the I/O queue fed by the now deprecated
570	function transfer().
571	
572	That queue could be purely conceptual.  For example, a driver used only
573	for low-frequency sensor access might be fine using synchronous PIO.
574	
575	But the queue will probably be very real, using message->queue, PIO,
576	often DMA (especially if the root filesystem is in SPI flash), and
577	execution contexts like IRQ handlers, tasklets, or workqueues (such
578	as keventd).  Your driver can be as fancy, or as simple, as you need.
579	Such a transfer() method would normally just add the message to a
580	queue, and then start some asynchronous transfer engine (unless it's
581	already running).
582	
583	
584	THANKS TO
585	---------
586	Contributors to Linux-SPI discussions include (in alphabetical order,
587	by last name):
588	
589	David Brownell
590	Russell King
591	Dmitry Pervushin
592	Stephen Street
593	Mark Underwood
594	Andrew Victor
595	Vitaly Wool
596	Grant Likely
597	Mark Brown
598	Linus Walleij
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