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Documentation / video4linux / cx2341x / fw-memory.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:04 EST.

1	This document describes the cx2341x memory map and documents some of the register
2	space.
3	
4	Note: the memory long words are little-endian ('intel format').
5	
6	Warning! This information was figured out from searching through the memory and
7	registers, this information may not be correct and is certainly not complete, and
8	was not derived from anything more than searching through the memory space with
9	commands like:
10	
11		ivtvctl -O min=0x02000000,max=0x020000ff
12	
13	So take this as is, I'm always searching for more stuff, it's a large
14	register space :-).
15	
16	Memory Map
17	==========
18	
19	The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
20	(Base Address Register 0). The addresses here are offsets relative to the
21	address held in BAR0.
22	
23	0x00000000-0x00ffffff Encoder memory space
24	0x00000000-0x0003ffff Encode.rom
25	      ???-???         MPEG buffer(s)
26	      ???-???         Raw video capture buffer(s)
27	      ???-???         Raw audio capture buffer(s)
28	      ???-???         Display buffers (6 or 9)
29	
30	0x01000000-0x01ffffff Decoder memory space
31	0x01000000-0x0103ffff Decode.rom
32	      ???-???         MPEG buffers(s)
33	0x0114b000-0x0115afff Audio.rom (deprecated?)
34	
35	0x02000000-0x0200ffff Register Space
36	
37	Registers
38	=========
39	
40	The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
41	All of these registers are 32 bits wide.
42	
43	DMA Registers 0x000-0xff:
44	
45	 0x00 - Control:
46		0=reset/cancel, 1=read, 2=write, 4=stop
47	 0x04 - DMA status:
48		1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
49	 0x08 - pci DMA pointer for read link list
50	 0x0c - pci DMA pointer for write link list
51	 0x10 - read/write DMA enable:
52		1=read enable, 2=write enable
53	 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
54	 0x18 - ??
55	 0x1c - always 0x20 or 32, smaller values slow down DMA transactions
56	 0x20 - always value of 0x780a010a
57	 0x24-0x3c - usually just random values???
58	 0x40 - Interrupt status
59	 0x44 - Write a bit here and shows up in Interrupt status 0x40
60	 0x48 - Interrupt Mask
61	 0x4C - always value of 0xfffdffff,
62		if changed to 0xffffffff DMA write interrupts break.
63	 0x50 - always 0xffffffff
64	 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
65		3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
66		interrupt masks???).
67	 0x60-0x7C - random values
68	 0x80 - first write linked list reg, for Encoder Memory addr
69	 0x84 - first write linked list reg, for pci memory addr
70	 0x88 - first write linked list reg, for length of buffer in memory addr
71		(|0x80000000 or this for last link)
72	 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
73		from linked list addr in reg 0x0c, firmware must push through or
74		something.
75	 0xe0 - first (and only) read linked list reg, for pci memory addr
76	 0xe4 - first (and only) read linked list reg, for Decoder memory addr
77	 0xe8 - first (and only) read linked list reg, for length of buffer
78	 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
79	
80	Memory locations for Encoder Buffers 0x700-0x7ff:
81	
82	These registers show offsets of memory locations pertaining to each
83	buffer area used for encoding, have to shift them by <<1 first.
84	
85	0x07F8: Encoder SDRAM refresh
86	0x07FC: Encoder SDRAM pre-charge
87	
88	Memory locations for Decoder Buffers 0x800-0x8ff:
89	
90	These registers show offsets of memory locations pertaining to each
91	buffer area used for decoding, have to shift them by <<1 first.
92	
93	0x08F8: Decoder SDRAM refresh
94	0x08FC: Decoder SDRAM pre-charge
95	
96	Other memory locations:
97	
98	0x2800: Video Display Module control
99	0x2D00: AO (audio output?) control
100	0x2D24: Bytes Flushed
101	0x7000: LSB I2C write clock bit (inverted)
102	0x7004: LSB I2C write data bit (inverted)
103	0x7008: LSB I2C read clock bit
104	0x700c: LSB I2C read data bit
105	0x9008: GPIO get input state
106	0x900c: GPIO set output state
107	0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
108	0x9050: SPU control
109	0x9054: Reset HW blocks
110	0x9058: VPU control
111	0xA018: Bit6: interrupt pending?
112	0xA064: APU command
113	
114	
115	Interrupt Status Register
116	=========================
117	
118	The definition of the bits in the interrupt status register 0x0040, and the
119	interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
120	execute.
121	
122	Bit
123	31 Encoder Start Capture
124	30 Encoder EOS
125	29 Encoder VBI capture
126	28 Encoder Video Input Module reset event
127	27 Encoder DMA complete
128	24 Decoder audio mode change detection event (through event notification)
129	22 Decoder data request
130	20 Decoder DMA complete
131	19 Decoder VBI re-insertion
132	18 Decoder DMA err (linked-list bad)
133	
134	Missing
135	Encoder API call completed
136	Decoder API call completed
137	Encoder API post(?)
138	Decoder API post(?)
139	Decoder VTRACE event
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