Based on kernel version 4.7.2. Page generated on 2016-08-22 22:39 EST.
1 Booting AArch64 Linux 2 ===================== 3 4 Author: Will Deacon <email@example.com> 5 Date : 07 September 2012 6 7 This document is based on the ARM booting document by Russell King and 8 is relevant to all public releases of the AArch64 Linux kernel. 9 10 The AArch64 exception model is made up of a number of exception levels 11 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure 12 counterpart. EL2 is the hypervisor level and exists only in non-secure 13 mode. EL3 is the highest priority level and exists only in secure mode. 14 15 For the purposes of this document, we will use the term `boot loader' 16 simply to define all software that executes on the CPU(s) before control 17 is passed to the Linux kernel. This may include secure monitor and 18 hypervisor code, or it may just be a handful of instructions for 19 preparing a minimal boot environment. 20 21 Essentially, the boot loader should provide (as a minimum) the 22 following: 23 24 1. Setup and initialise the RAM 25 2. Setup the device tree 26 3. Decompress the kernel image 27 4. Call the kernel image 28 29 30 1. Setup and initialise RAM 31 --------------------------- 32 33 Requirement: MANDATORY 34 35 The boot loader is expected to find and initialise all RAM that the 36 kernel will use for volatile data storage in the system. It performs 37 this in a machine dependent manner. (It may use internal algorithms 38 to automatically locate and size all RAM, or it may use knowledge of 39 the RAM in the machine, or any other method the boot loader designer 40 sees fit.) 41 42 43 2. Setup the device tree 44 ------------------------- 45 46 Requirement: MANDATORY 47 48 The device tree blob (dtb) must be placed on an 8-byte boundary and must 49 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable 50 using blocks of up to 2 megabytes in size, it must not be placed within 51 any 2M region which must be mapped with any specific attributes. 52 53 NOTE: versions prior to v4.2 also require that the DTB be placed within 54 the 512 MB region starting at text_offset bytes below the kernel Image. 55 56 3. Decompress the kernel image 57 ------------------------------ 58 59 Requirement: OPTIONAL 60 61 The AArch64 kernel does not currently provide a decompressor and 62 therefore requires decompression (gzip etc.) to be performed by the boot 63 loader if a compressed Image target (e.g. Image.gz) is used. For 64 bootloaders that do not implement this requirement, the uncompressed 65 Image target is available instead. 66 67 68 4. Call the kernel image 69 ------------------------ 70 71 Requirement: MANDATORY 72 73 The decompressed kernel image contains a 64-byte header as follows: 74 75 u32 code0; /* Executable code */ 76 u32 code1; /* Executable code */ 77 u64 text_offset; /* Image load offset, little endian */ 78 u64 image_size; /* Effective Image size, little endian */ 79 u64 flags; /* kernel flags, little endian */ 80 u64 res2 = 0; /* reserved */ 81 u64 res3 = 0; /* reserved */ 82 u64 res4 = 0; /* reserved */ 83 u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */ 84 u32 res5; /* reserved (used for PE COFF offset) */ 85 86 87 Header notes: 88 89 - As of v3.17, all fields are little endian unless stated otherwise. 90 91 - code0/code1 are responsible for branching to stext. 92 93 - when booting through EFI, code0/code1 are initially skipped. 94 res5 is an offset to the PE header and the PE header has the EFI 95 entry point (efi_stub_entry). When the stub has done its work, it 96 jumps to code0 to resume the normal boot process. 97 98 - Prior to v3.17, the endianness of text_offset was not specified. In 99 these cases image_size is zero and text_offset is 0x80000 in the 100 endianness of the kernel. Where image_size is non-zero image_size is 101 little-endian and must be respected. Where image_size is zero, 102 text_offset can be assumed to be 0x80000. 103 104 - The flags field (introduced in v3.17) is a little-endian 64-bit field 105 composed as follows: 106 Bit 0: Kernel endianness. 1 if BE, 0 if LE. 107 Bit 1-2: Kernel Page size. 108 0 - Unspecified. 109 1 - 4K 110 2 - 16K 111 3 - 64K 112 Bit 3: Kernel physical placement 113 0 - 2MB aligned base should be as close as possible 114 to the base of DRAM, since memory below it is not 115 accessible via the linear mapping 116 1 - 2MB aligned base may be anywhere in physical 117 memory 118 Bits 4-63: Reserved. 119 120 - When image_size is zero, a bootloader should attempt to keep as much 121 memory as possible free for use by the kernel immediately after the 122 end of the kernel image. The amount of space required will vary 123 depending on selected features, and is effectively unbound. 124 125 The Image must be placed text_offset bytes from a 2MB aligned base 126 address anywhere in usable system RAM and called there. The region 127 between the 2 MB aligned base address and the start of the image has no 128 special significance to the kernel, and may be used for other purposes. 129 At least image_size bytes from the start of the image must be free for 130 use by the kernel. 131 NOTE: versions prior to v4.6 cannot make use of memory below the 132 physical offset of the Image so it is recommended that the Image be 133 placed as close as possible to the start of system RAM. 134 135 If an initrd/initramfs is passed to the kernel at boot, it must reside 136 entirely within a 1 GB aligned physical memory window of up to 32 GB in 137 size that fully covers the kernel Image as well. 138 139 Any memory described to the kernel (even that below the start of the 140 image) which is not marked as reserved from the kernel (e.g., with a 141 memreserve region in the device tree) will be considered as available to 142 the kernel. 143 144 Before jumping into the kernel, the following conditions must be met: 145 146 - Quiesce all DMA capable devices so that memory does not get 147 corrupted by bogus network packets or disk data. This will save 148 you many hours of debug. 149 150 - Primary CPU general-purpose register settings 151 x0 = physical address of device tree blob (dtb) in system RAM. 152 x1 = 0 (reserved for future use) 153 x2 = 0 (reserved for future use) 154 x3 = 0 (reserved for future use) 155 156 - CPU mode 157 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, 158 IRQ and FIQ). 159 The CPU must be in either EL2 (RECOMMENDED in order to have access to 160 the virtualisation extensions) or non-secure EL1. 161 162 - Caches, MMUs 163 The MMU must be off. 164 Instruction cache may be on or off. 165 The address range corresponding to the loaded kernel image must be 166 cleaned to the PoC. In the presence of a system cache or other 167 coherent masters with caches enabled, this will typically require 168 cache maintenance by VA rather than set/way operations. 169 System caches which respect the architected cache maintenance by VA 170 operations must be configured and may be enabled. 171 System caches which do not respect architected cache maintenance by VA 172 operations (not recommended) must be configured and disabled. 173 174 - Architected timers 175 CNTFRQ must be programmed with the timer frequency and CNTVOFF must 176 be programmed with a consistent value on all CPUs. If entering the 177 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where 178 available. 179 180 - Coherency 181 All CPUs to be booted by the kernel must be part of the same coherency 182 domain on entry to the kernel. This may require IMPLEMENTATION DEFINED 183 initialisation to enable the receiving of maintenance operations on 184 each CPU. 185 186 - System registers 187 All writable architected system registers at the exception level where 188 the kernel image will be entered must be initialised by software at a 189 higher exception level to prevent execution in an UNKNOWN state. 190 191 For systems with a GICv3 interrupt controller to be used in v3 mode: 192 - If EL3 is present: 193 ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. 194 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. 195 - If the kernel is entered at EL1: 196 ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1 197 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1. 198 - The DT or ACPI tables must describe a GICv3 interrupt controller. 199 200 For systems with a GICv3 interrupt controller to be used in 201 compatibility (v2) mode: 202 - If EL3 is present: 203 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0. 204 - If the kernel is entered at EL1: 205 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. 206 - The DT or ACPI tables must describe a GICv2 interrupt controller. 207 208 The requirements described above for CPU mode, caches, MMUs, architected 209 timers, coherency and system registers apply to all CPUs. All CPUs must 210 enter the kernel in the same exception level. 211 212 The boot loader is expected to enter the kernel on each CPU in the 213 following manner: 214 215 - The primary CPU must jump directly to the first instruction of the 216 kernel image. The device tree blob passed by this CPU must contain 217 an 'enable-method' property for each cpu node. The supported 218 enable-methods are described below. 219 220 It is expected that the bootloader will generate these device tree 221 properties and insert them into the blob prior to kernel entry. 222 223 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr' 224 property in their cpu node. This property identifies a 225 naturally-aligned 64-bit zero-initalised memory location. 226 227 These CPUs should spin outside of the kernel in a reserved area of 228 memory (communicated to the kernel by a /memreserve/ region in the 229 device tree) polling their cpu-release-addr location, which must be 230 contained in the reserved region. A wfe instruction may be inserted 231 to reduce the overhead of the busy-loop and a sev will be issued by 232 the primary CPU. When a read of the location pointed to by the 233 cpu-release-addr returns a non-zero value, the CPU must jump to this 234 value. The value will be written as a single 64-bit little-endian 235 value, so CPUs must convert the read value to their native endianness 236 before jumping to it. 237 238 - CPUs with a "psci" enable method should remain outside of 239 the kernel (i.e. outside of the regions of memory described to the 240 kernel in the memory node, or in a reserved area of memory described 241 to the kernel by a /memreserve/ region in the device tree). The 242 kernel will issue CPU_ON calls as described in ARM document number ARM 243 DEN 0022A ("Power State Coordination Interface System Software on ARM 244 processors") to bring CPUs into the kernel. 245 246 The device tree should contain a 'psci' node, as described in 247 Documentation/devicetree/bindings/arm/psci.txt. 248 249 - Secondary CPU general-purpose register settings 250 x0 = 0 (reserved for future use) 251 x1 = 0 (reserved for future use) 252 x2 = 0 (reserved for future use) 253 x3 = 0 (reserved for future use)