Based on kernel version 6.9. Page generated on 2024-05-14 10:02 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 | # SPDX-License-Identifier: GPL-2.0-only # Copyright 2019-2020, The Linux Foundation, All Rights Reserved %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/gmu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: GMU attached to certain Adreno GPUs maintainers: - Rob Clark <robdclark@gmail.com> description: | These bindings describe the Graphics Management Unit (GMU) that is attached to members of the Adreno A6xx GPU family. The GMU provides on-device power management and support to improve power efficiency and reduce the load on the CPU. properties: compatible: oneOf: - items: - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - const: qcom,adreno-gmu-wrapper reg: minItems: 1 maxItems: 4 reg-names: minItems: 1 maxItems: 4 clocks: minItems: 4 maxItems: 7 clock-names: minItems: 4 maxItems: 7 interrupts: items: - description: GMU HFI interrupt - description: GMU interrupt interrupt-names: items: - const: hfi - const: gmu power-domains: items: - description: CX power domain - description: GX power domain power-domain-names: items: - const: cx - const: gx iommus: maxItems: 1 qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM operating-points-v2: true opp-table: type: object required: - compatible - reg - reg-names - power-domains - power-domain-names additionalProperties: false allOf: - if: properties: compatible: contains: enum: - qcom,adreno-gmu-618.0 - qcom,adreno-gmu-630.2 then: properties: reg: items: - description: Core GMU registers - description: GMU PDC registers - description: GMU PDC sequence registers reg-names: items: - const: gmu - const: gmu_pdc - const: gmu_pdc_seq clocks: items: - description: GMU clock - description: GPU CX clock - description: GPU AXI clock - description: GPU MEMNOC clock clock-names: items: - const: gmu - const: cxo - const: axi - const: memnoc - if: properties: compatible: contains: enum: - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 then: properties: reg: items: - description: Core GMU registers - description: Resource controller registers - description: GMU PDC registers reg-names: items: - const: gmu - const: rscc - const: gmu_pdc clocks: items: - description: GMU clock - description: GPU CX clock - description: GPU AXI clock - description: GPU MEMNOC clock - description: GPU AHB clock - description: GPU HUB CX clock - description: GPU SMMU vote clock clock-names: items: - const: gmu - const: cxo - const: axi - const: memnoc - const: ahb - const: hub - const: smmu_vote - if: properties: compatible: contains: enum: - qcom,adreno-gmu-640.1 then: properties: reg: items: - description: Core GMU registers - description: GMU PDC registers - description: GMU PDC sequence registers reg-names: items: - const: gmu - const: gmu_pdc - const: gmu_pdc_seq - if: properties: compatible: contains: enum: - qcom,adreno-gmu-650.2 then: properties: reg: items: - description: Core GMU registers - description: Resource controller registers - description: GMU PDC registers - description: GMU PDC sequence registers reg-names: items: - const: gmu - const: rscc - const: gmu_pdc - const: gmu_pdc_seq - if: properties: compatible: contains: enum: - qcom,adreno-gmu-640.1 - qcom,adreno-gmu-650.2 then: properties: clocks: items: - description: GPU AHB clock - description: GMU clock - description: GPU CX clock - description: GPU AXI clock - description: GPU MEMNOC clock clock-names: items: - const: ahb - const: gmu - const: cxo - const: axi - const: memnoc - if: properties: compatible: contains: enum: - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 - qcom,adreno-gmu-750.1 then: properties: reg: items: - description: Core GMU registers - description: Resource controller registers - description: GMU PDC registers reg-names: items: - const: gmu - const: rscc - const: gmu_pdc clocks: items: - description: GPU AHB clock - description: GMU clock - description: GPU CX clock - description: GPU AXI clock - description: GPU MEMNOC clock - description: GMU HUB clock - description: GPUSS DEMET clock clock-names: items: - const: ahb - const: gmu - const: cxo - const: axi - const: memnoc - const: hub - const: demet required: - qcom,qmp - if: properties: compatible: contains: const: qcom,adreno-gmu-wrapper then: properties: reg: items: - description: GMU wrapper register space reg-names: items: - const: gmu else: required: - clocks - clock-names - interrupts - interrupt-names - iommus - operating-points-v2 examples: - | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> gmu: gmu@506a000 { compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0x506a000 0x30000>, <0xb280000 0x10000>, <0xb480000 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; gmu_wrapper: gmu@596a000 { compatible = "qcom,adreno-gmu-wrapper"; reg = <0x0596a000 0x30000>; reg-names = "gmu"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; }; |