# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC8280XP Display Processing Unit

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  Device tree bindings for SC8280XP Display Processing Unit.

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    const: qcom,sc8280xp-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display ahb clock
      - description: Display lut clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: bus
      - const: nrt_bus
      - const: iface
      - const: lut
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sc8280xp.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
 
    display-controller@ae01000 {
        compatible = "qcom,sc8280xp-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;
        reg-names = "mdp", "vbif";
 
        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&gcc GCC_DISP_SF_AXI_CLK>,
                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus",
                      "nrt_bus",
                      "iface",
                      "lut",
                      "core",
                      "vsync";
 
        assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
        assigned-clock-rates = <460000000>,
                               <19200000>;
 
        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmhpd SC8280XP_MMCX>;
 
        interrupt-parent = <&mdss0>;
        interrupts = <0>;
 
        ports {
            #address-cells = <1>;
            #size-cells = <0>;
 
            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&mdss0_dp0_in>;
                };
            };
 
            port@4 {
                reg = <4>;
                endpoint {
                    remote-endpoint = <&mdss0_dp1_in>;
                };
            };
 
            port@5 {
                reg = <5>;
                endpoint {
                    remote-endpoint = <&mdss0_dp3_in>;
                };
            };
 
            port@6 {
                reg = <6>;
                endpoint {
                    remote-endpoint = <&mdss0_dp2_in>;
                };
            };
        };
    };
...