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Documentation / devicetree / bindings / gpio / gpio-mvebu.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Marvell EBU GPIO controller
2	
3	Required properties:
4	
5	- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6	  "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
7	
8	    "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9	    Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
10	    should be used for the Discovery MV78200.
11	
12	    "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
13	    (MV78230, MV78260, MV78460).
14	
15	    "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
16	    SoCs (either from AP or CP), see
17	    Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
18	    and
19	    Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
20	    for specific details about the offset property.
21	
22	- reg: Address and length of the register set for the device. Only one
23	  entry is expected, except for the "marvell,armadaxp-gpio" variant
24	  for which two entries are expected: one for the general registers,
25	  one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
26	
27	- interrupts: The list of interrupts that are used for all the pins
28	  managed by this GPIO bank. There can be more than one interrupt
29	  (example: 1 interrupt per 8 pins on Armada XP, which means 4
30	  interrupts per bank of 32 GPIOs).
31	
32	- interrupt-controller: identifies the node as an interrupt controller
33	
34	- #interrupt-cells: specifies the number of cells needed to encode an
35	  interrupt source. Should be two.
36	  The first cell is the GPIO number.
37	  The second cell is used to specify flags:
38	    bits[3:0] trigger type and level flags:
39	      1 = low-to-high edge triggered.
40	      2 = high-to-low edge triggered.
41	      4 = active high level-sensitive.
42	      8 = active low level-sensitive.
43	
44	- gpio-controller: marks the device node as a gpio controller
45	
46	- ngpios: number of GPIOs this controller has
47	
48	- #gpio-cells: Should be two. The first cell is the pin number. The
49	  second cell is reserved for flags, unused at the moment.
50	
51	Optional properties:
52	
53	In order to use the GPIO lines in PWM mode, some additional optional
54	properties are required.
55	
56	- compatible: Must contain "marvell,armada-370-gpio"
57	
58	- reg: an additional register set is needed, for the GPIO Blink
59	  Counter on/off registers.
60	
61	- reg-names: Must contain an entry "pwm" corresponding to the
62	  additional register range needed for PWM operation.
63	
64	- #pwm-cells: Should be two. The first cell is the GPIO line number. The
65	  second cell is the period in nanoseconds.
66	
67	- clocks: Must be a phandle to the clock for the GPIO controller.
68	
69	Example:
70	
71			gpio0: gpio@d0018100 {
72				compatible = "marvell,armadaxp-gpio";
73				reg = <0xd0018100 0x40>,
74				    <0xd0018800 0x30>;
75				ngpios = <32>;
76				gpio-controller;
77				#gpio-cells = <2>;
78				interrupt-controller;
79				#interrupt-cells = <2>;
80				interrupts = <16>, <17>, <18>, <19>;
81			};
82	
83			gpio1: gpio@18140 {
84				compatible = "marvell,armada-370-gpio";
85				reg = <0x18140 0x40>, <0x181c8 0x08>;
86				reg-names = "gpio", "pwm";
87				ngpios = <17>;
88				gpio-controller;
89				#gpio-cells = <2>;
90				#pwm-cells = <2>;
91				interrupt-controller;
92				#interrupt-cells = <2>;
93				interrupts = <87>, <88>, <89>;
94				clocks = <&coreclk 0>;
95			};
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