Based on kernel version 6.0.19
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mellanox I2C SMBus on BlueField SoCs maintainers: - Khalil Blaiech <kblaiech@nvidia.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# properties: compatible: enum: - mellanox,i2c-mlxbf1 - mellanox,i2c-mlxbf2 reg: minItems: 3 items: - description: Smbus block registers - description: Cause master registers - description: Cause slave registers - description: Cause coalesce registers interrupts: maxItems: 1 clock-frequency: enum: [ 100000, 400000, 1000000 ] description: bus frequency used to configure timing registers; The frequency is expressed in Hz. Default is 100000. required: - compatible - reg - interrupts unevaluatedProperties: false if: properties: compatible: contains: enum: - mellanox,i2c-mlxbf1 then: properties: reg: maxItems: 3 examples: - | i2c@2804000 { compatible = "mellanox,i2c-mlxbf1"; reg = <0x02804000 0x800>, <0x02801200 0x020>, <0x02801260 0x020>; interrupts = <57>; clock-frequency = <100000>; }; - | i2c@2808800 { compatible = "mellanox,i2c-mlxbf2"; reg = <0x02808800 0x600>, <0x02808e00 0x020>, <0x02808e20 0x020>, <0x02808e40 0x010>; interrupts = <57>; clock-frequency = <400000>; }; |