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Documentation / devicetree / bindings / spi / spi-bus.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	SPI (Serial Peripheral Interface) busses
2	
3	SPI busses can be described with a node for the SPI controller device
4	and a set of child nodes for each SPI slave on the bus.  The system's SPI
5	controller may be described for use in SPI master mode or in SPI slave mode,
6	but not for both at the same time.
7	
8	The SPI controller node requires the following properties:
9	- compatible      - Name of SPI bus controller following generic names
10			    recommended practice.
11	
12	In master mode, the SPI controller node requires the following additional
13	properties:
14	- #address-cells  - number of cells required to define a chip select
15			address on the SPI bus.
16	- #size-cells     - should be zero.
17	
18	In slave mode, the SPI controller node requires one additional property:
19	- spi-slave       - Empty property.
20	
21	No other properties are required in the SPI bus node.  It is assumed
22	that a driver for an SPI bus device will understand that it is an SPI bus.
23	However, the binding does not attempt to define the specific method for
24	assigning chip select numbers.  Since SPI chip select configuration is
25	flexible and non-standardized, it is left out of this binding with the
26	assumption that board specific platform code will be used to manage
27	chip selects.  Individual drivers can define additional properties to
28	support describing the chip select layout.
29	
30	Optional properties (master mode only):
31	- cs-gpios	  - gpios chip select.
32	- num-cs	  - total number of chipselects.
33	
34	If cs-gpios is used the number of chip selects will be increased automatically
35	with max(cs-gpios > hw cs).
36	
37	So if for example the controller has 2 CS lines, and the cs-gpios
38	property looks like this:
39	
40	cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
41	
42	Then it should be configured so that num_chipselect = 4 with the
43	following mapping:
44	
45	cs0 : &gpio1 0 0
46	cs1 : native
47	cs2 : &gpio1 1 0
48	cs3 : &gpio1 2 0
49	
50	
51	SPI slave nodes must be children of the SPI controller node.
52	
53	In master mode, one or more slave nodes (up to the number of chip selects) can
54	be present.  Required properties are:
55	- compatible      - Name of SPI device following generic names recommended
56			    practice.
57	- reg             - Chip select address of device.
58	- spi-max-frequency - Maximum SPI clocking speed of device in Hz.
59	
60	In slave mode, the (single) slave node is optional.
61	If present, it must be called "slave".  Required properties are:
62	- compatible      - Name of SPI device following generic names recommended
63			    practice.
64	
65	All slave nodes can contain the following optional properties:
66	- spi-cpol        - Empty property indicating device requires inverse clock
67			    polarity (CPOL) mode.
68	- spi-cpha        - Empty property indicating device requires shifted clock
69			    phase (CPHA) mode.
70	- spi-cs-high     - Empty property indicating device requires chip select
71			    active high.
72	- spi-3wire       - Empty property indicating device requires 3-wire mode.
73	- spi-lsb-first   - Empty property indicating device requires LSB first mode.
74	- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
75			    Defaults to 1 if not present.
76	- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
77			    Defaults to 1 if not present.
78	- spi-rx-delay-us - Microsecond delay after a read transfer.
79	- spi-tx-delay-us - Microsecond delay after a write transfer.
80	
81	Some SPI controllers and devices support Dual and Quad SPI transfer mode.
82	It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
83	wires (QUAD).
84	Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
85	only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
86	Dual/Quad mode is not allowed when 3-wire mode is used.
87	
88	If a gpio chipselect is used for the SPI slave the gpio number will be passed
89	via the SPI master node cs-gpios property.
90	
91	SPI example for an MPC5200 SPI bus:
92		spi@f00 {
93			#address-cells = <1>;
94			#size-cells = <0>;
95			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
96			reg = <0xf00 0x20>;
97			interrupts = <2 13 0 2 14 0>;
98			interrupt-parent = <&mpc5200_pic>;
99	
100			ethernet-switch@0 {
101				compatible = "micrel,ks8995m";
102				spi-max-frequency = <1000000>;
103				reg = <0>;
104			};
105	
106			codec@1 {
107				compatible = "ti,tlv320aic26";
108				spi-max-frequency = <100000>;
109				reg = <1>;
110			};
111		};
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