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Documentation / devicetree / bindings / spi / spi-bus.txt




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Based on kernel version 4.9. Page generated on 2016-12-21 14:33 EST.

1	SPI (Serial Peripheral Interface) busses
2	
3	SPI busses can be described with a node for the SPI master device
4	and a set of child nodes for each SPI slave on the bus.  For this
5	discussion, it is assumed that the system's SPI controller is in
6	SPI master mode.  This binding does not describe SPI controllers
7	in slave mode.
8	
9	The SPI master node requires the following properties:
10	- #address-cells  - number of cells required to define a chip select
11			address on the SPI bus.
12	- #size-cells     - should be zero.
13	- compatible      - name of SPI bus controller following generic names
14			recommended practice.
15	No other properties are required in the SPI bus node.  It is assumed
16	that a driver for an SPI bus device will understand that it is an SPI bus.
17	However, the binding does not attempt to define the specific method for
18	assigning chip select numbers.  Since SPI chip select configuration is
19	flexible and non-standardized, it is left out of this binding with the
20	assumption that board specific platform code will be used to manage
21	chip selects.  Individual drivers can define additional properties to
22	support describing the chip select layout.
23	
24	Optional properties:
25	- cs-gpios	  - gpios chip select.
26	- num-cs	  - total number of chipselects.
27	
28	If cs-gpios is used the number of chip selects will be increased automatically
29	with max(cs-gpios > hw cs).
30	
31	So if for example the controller has 2 CS lines, and the cs-gpios
32	property looks like this:
33	
34	cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
35	
36	Then it should be configured so that num_chipselect = 4 with the
37	following mapping:
38	
39	cs0 : &gpio1 0 0
40	cs1 : native
41	cs2 : &gpio1 1 0
42	cs3 : &gpio1 2 0
43	
44	SPI slave nodes must be children of the SPI master node and can
45	contain the following properties.
46	- reg             - (required) chip select address of device.
47	- compatible      - (required) name of SPI device following generic names
48			recommended practice.
49	- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz.
50	- spi-cpol        - (optional) Empty property indicating device requires
51			inverse clock polarity (CPOL) mode.
52	- spi-cpha        - (optional) Empty property indicating device requires
53			shifted clock phase (CPHA) mode.
54	- spi-cs-high     - (optional) Empty property indicating device requires
55			chip select active high.
56	- spi-3wire       - (optional) Empty property indicating device requires
57			3-wire mode.
58	- spi-lsb-first   - (optional) Empty property indicating device requires
59			LSB first mode.
60	- spi-tx-bus-width - (optional) The bus width (number of data wires) that is
61	                      used for MOSI. Defaults to 1 if not present.
62	- spi-rx-bus-width - (optional) The bus width (number of data wires) that is
63	                      used for MISO. Defaults to 1 if not present.
64	- spi-rx-delay-us  - (optional) Microsecond delay after a read transfer.
65	- spi-tx-delay-us  - (optional) Microsecond delay after a write transfer.
66	
67	Some SPI controllers and devices support Dual and Quad SPI transfer mode.
68	It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
69	wires (QUAD).
70	Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
71	only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
72	Dual/Quad mode is not allowed when 3-wire mode is used.
73	
74	If a gpio chipselect is used for the SPI slave the gpio number will be passed
75	via the SPI master node cs-gpios property.
76	
77	SPI example for an MPC5200 SPI bus:
78		spi@f00 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
82			reg = <0xf00 0x20>;
83			interrupts = <2 13 0 2 14 0>;
84			interrupt-parent = <&mpc5200_pic>;
85	
86			ethernet-switch@0 {
87				compatible = "micrel,ks8995m";
88				spi-max-frequency = <1000000>;
89				reg = <0>;
90			};
91	
92			codec@1 {
93				compatible = "ti,tlv320aic26";
94				spi-max-frequency = <100000>;
95				reg = <1>;
96			};
97		};
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