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Documentation / devicetree / bindings / spi / spi-fsl-dspi.txt




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Based on kernel version 4.8. Page generated on 2016-10-06 23:14 EST.

1	ARM Freescale DSPI controller
2	
3	Required properties:
4	- compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5			"fsl,ls2085a-dspi"
6			or
7			"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8	- reg : Offset and length of the register set for the device
9	- interrupts : Should contain SPI controller interrupt
10	- clocks: from common clock binding: handle to dspi clock.
11	- clock-names: from common clock binding: Shall be "dspi".
12	- pinctrl-0: pin control group to be used for this controller.
13	- pinctrl-names: must contain a "default" entry.
14	- spi-num-chipselects : the number of the chipselect signals.
15	- bus-num : the slave chip chipselect signal number.
16	
17	Optional property:
18	- big-endian: If present the dspi device's registers are implemented
19	  in big endian mode.
20	
21	Optional SPI slave node properties:
22	- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
23	  select and the start of clock signal, at the start of a transfer.
24	- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
25	  signal and deactivating chip select, at the end of a transfer.
26	
27	Example:
28	
29	dspi0@4002c000 {
30		#address-cells = <1>;
31		#size-cells = <0>;
32		compatible = "fsl,vf610-dspi";
33		reg = <0x4002c000 0x1000>;
34		interrupts = <0 67 0x04>;
35		clocks = <&clks VF610_CLK_DSPI0>;
36		clock-names = "dspi";
37		spi-num-chipselects = <5>;
38		bus-num = <0>;
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_dspi0_1>;
41		big-endian;
42		status = "okay";
43	
44		sflash: at26df081a@0 {
45			#address-cells = <1>;
46			#size-cells = <1>;
47			compatible = "atmel,at26df081a";
48			spi-max-frequency = <16000000>;
49			spi-cpol;
50			spi-cpha;
51			reg = <0>;
52			linux,modalias = "m25p80";
53			modal = "at26df081a";
54			fsl,spi-cs-sck-delay = <100>;
55			fsl,spi-sck-cs-delay = <50>;
56		};
57	};
58	
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