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Documentation / ia64 / IRQ-redir.txt

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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	IRQ affinity on IA64 platforms
2	------------------------------
3	                           07.01.2002, Erich Focht <efocht@ess.nec.de>
6	By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
7	controlled. The behavior on IA64 platforms is slightly different from
8	that described in Documentation/IRQ-affinity.txt for i386 systems.
10	Because of the usage of SAPIC mode and physical destination mode the
11	IRQ target is one particular CPU and cannot be a mask of several
12	CPUs. Only the first non-zero bit is taken into account.
15	Usage examples:
17	The target CPU has to be specified as a hexadecimal CPU mask. The
18	first non-zero bit is the selected CPU. This format has been kept for
19	compatibility reasons with i386.
21	Set the delivery mode of interrupt 41 to fixed and route the
22	interrupts to CPU #3 (logical CPU number) (2^3=0x08):
23	     echo "8" >/proc/irq/41/smp_affinity
25	Set the default route for IRQ number 41 to CPU 6 in lowest priority
26	delivery mode (redirectable):
27	     echo "r 40" >/proc/irq/41/smp_affinity
29	The output of the command
30	     cat /proc/irq/IRQ#/smp_affinity
31	gives the target CPU mask for the specified interrupt vector. If the CPU
32	mask is preceded by the character "r", the interrupt is redirectable
33	(i.e. lowest priority mode routing is used), otherwise its route is
34	fixed.
38	Initialization and default behavior:
40	If the platform features IRQ redirection (info provided by SAL) all
41	IO-SAPIC interrupts are initialized with CPU#0 as their default target
42	and the routing is the so called "lowest priority mode" (actually
43	fixed SAPIC mode with hint). The XTP chipset registers are used as hints
44	for the IRQ routing. Currently in Linux XTP registers can have three
45	values:
46		- minimal for an idle task,
47		- normal if any other task runs,
48		- maximal if the CPU is going to be switched off.
49	The IRQ is routed to the CPU with lowest XTP register value, the
50	search begins at the default CPU. Therefore most of the interrupts
51	will be handled by CPU #0.
53	If the platform doesn't feature interrupt redirection IOSAPIC fixed
54	routing is used. The target CPUs are distributed in a round robin
55	manner. IRQs will be routed only to the selected target CPUs. Check
56	with
57	        cat /proc/interrupts
63	On large (multi-node) systems it is recommended to route the IRQs to
64	the node to which the corresponding device is connected.
65	For systems like the NEC AzusA we get IRQ node-affinity for free. This
66	is because usually the chipsets on each node redirect the interrupts
67	only to their own CPUs (as they cannot see the XTP registers on the
68	other nodes).
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