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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1				Booting AArch64 Linux
2				=====================
4	Author: Will Deacon <will.deacon@arm.com>
5	Date  : 07 September 2012
7	This document is based on the ARM booting document by Russell King and
8	is relevant to all public releases of the AArch64 Linux kernel.
10	The AArch64 exception model is made up of a number of exception levels
11	(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
12	counterpart.  EL2 is the hypervisor level and exists only in non-secure
13	mode. EL3 is the highest priority level and exists only in secure mode.
15	For the purposes of this document, we will use the term `boot loader'
16	simply to define all software that executes on the CPU(s) before control
17	is passed to the Linux kernel.  This may include secure monitor and
18	hypervisor code, or it may just be a handful of instructions for
19	preparing a minimal boot environment.
21	Essentially, the boot loader should provide (as a minimum) the
22	following:
24	1. Setup and initialise the RAM
25	2. Setup the device tree
26	3. Decompress the kernel image
27	4. Call the kernel image
30	1. Setup and initialise RAM
31	---------------------------
33	Requirement: MANDATORY
35	The boot loader is expected to find and initialise all RAM that the
36	kernel will use for volatile data storage in the system.  It performs
37	this in a machine dependent manner.  (It may use internal algorithms
38	to automatically locate and size all RAM, or it may use knowledge of
39	the RAM in the machine, or any other method the boot loader designer
40	sees fit.)
43	2. Setup the device tree
44	-------------------------
46	Requirement: MANDATORY
48	The device tree blob (dtb) must be placed on an 8-byte boundary within
49	the first 512 megabytes from the start of the kernel image and must not
50	cross a 2-megabyte boundary. This is to allow the kernel to map the
51	blob using a single section mapping in the initial page tables.
54	3. Decompress the kernel image
55	------------------------------
57	Requirement: OPTIONAL
59	The AArch64 kernel does not currently provide a decompressor and
60	therefore requires decompression (gzip etc.) to be performed by the boot
61	loader if a compressed Image target (e.g. Image.gz) is used.  For
62	bootloaders that do not implement this requirement, the uncompressed
63	Image target is available instead.
66	4. Call the kernel image
67	------------------------
69	Requirement: MANDATORY
71	The decompressed kernel image contains a 64-byte header as follows:
73	  u32 code0;			/* Executable code */
74	  u32 code1;			/* Executable code */
75	  u64 text_offset;		/* Image load offset */
76	  u64 res0	= 0;		/* reserved */
77	  u64 res1	= 0;		/* reserved */
78	  u64 res2	= 0;		/* reserved */
79	  u64 res3	= 0;		/* reserved */
80	  u64 res4	= 0;		/* reserved */
81	  u32 magic	= 0x644d5241;	/* Magic number, little endian, "ARM\x64" */
82	  u32 res5 = 0;      		/* reserved */
85	Header notes:
87	- code0/code1 are responsible for branching to stext.
88	- when booting through EFI, code0/code1 are initially skipped.
89	  res5 is an offset to the PE header and the PE header has the EFI
90	  entry point (efi_stub_entry). When the stub has done its work, it
91	  jumps to code0 to resume the normal boot process.
93	The image must be placed at the specified offset (currently 0x80000)
94	from the start of the system RAM and called there. The start of the
95	system RAM must be aligned to 2MB.
97	Before jumping into the kernel, the following conditions must be met:
99	- Quiesce all DMA capable devices so that memory does not get
100	  corrupted by bogus network packets or disk data.  This will save
101	  you many hours of debug.
103	- Primary CPU general-purpose register settings
104	  x0 = physical address of device tree blob (dtb) in system RAM.
105	  x1 = 0 (reserved for future use)
106	  x2 = 0 (reserved for future use)
107	  x3 = 0 (reserved for future use)
109	- CPU mode
110	  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
111	  IRQ and FIQ).
112	  The CPU must be in either EL2 (RECOMMENDED in order to have access to
113	  the virtualisation extensions) or non-secure EL1.
115	- Caches, MMUs
116	  The MMU must be off.
117	  Instruction cache may be on or off.
118	  The address range corresponding to the loaded kernel image must be
119	  cleaned to the PoC. In the presence of a system cache or other
120	  coherent masters with caches enabled, this will typically require
121	  cache maintenance by VA rather than set/way operations.
122	  System caches which respect the architected cache maintenance by VA
123	  operations must be configured and may be enabled.
124	  System caches which do not respect architected cache maintenance by VA
125	  operations (not recommended) must be configured and disabled.
127	- Architected timers
128	  CNTFRQ must be programmed with the timer frequency and CNTVOFF must
129	  be programmed with a consistent value on all CPUs.  If entering the
130	  kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
131	  available.
133	- Coherency
134	  All CPUs to be booted by the kernel must be part of the same coherency
135	  domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
136	  initialisation to enable the receiving of maintenance operations on
137	  each CPU.
139	- System registers
140	  All writable architected system registers at the exception level where
141	  the kernel image will be entered must be initialised by software at a
142	  higher exception level to prevent execution in an UNKNOWN state.
144	The requirements described above for CPU mode, caches, MMUs, architected
145	timers, coherency and system registers apply to all CPUs.  All CPUs must
146	enter the kernel in the same exception level.
148	The boot loader is expected to enter the kernel on each CPU in the
149	following manner:
151	- The primary CPU must jump directly to the first instruction of the
152	  kernel image.  The device tree blob passed by this CPU must contain
153	  an 'enable-method' property for each cpu node.  The supported
154	  enable-methods are described below.
156	  It is expected that the bootloader will generate these device tree
157	  properties and insert them into the blob prior to kernel entry.
159	- CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
160	  property in their cpu node.  This property identifies a
161	  naturally-aligned 64-bit zero-initalised memory location.
163	  These CPUs should spin outside of the kernel in a reserved area of
164	  memory (communicated to the kernel by a /memreserve/ region in the
165	  device tree) polling their cpu-release-addr location, which must be
166	  contained in the reserved region.  A wfe instruction may be inserted
167	  to reduce the overhead of the busy-loop and a sev will be issued by
168	  the primary CPU.  When a read of the location pointed to by the
169	  cpu-release-addr returns a non-zero value, the CPU must jump to this
170	  value.  The value will be written as a single 64-bit little-endian
171	  value, so CPUs must convert the read value to their native endianness
172	  before jumping to it.
174	- CPUs with a "psci" enable method should remain outside of
175	  the kernel (i.e. outside of the regions of memory described to the
176	  kernel in the memory node, or in a reserved area of memory described
177	  to the kernel by a /memreserve/ region in the device tree).  The
178	  kernel will issue CPU_ON calls as described in ARM document number ARM
179	  DEN 0022A ("Power State Coordination Interface System Software on ARM
180	  processors") to bring CPUs into the kernel.
182	  The device tree should contain a 'psci' node, as described in
183	  Documentation/devicetree/bindings/arm/psci.txt.
185	- Secondary CPU general-purpose register settings
186	  x0 = 0 (reserved for future use)
187	  x1 = 0 (reserved for future use)
188	  x2 = 0 (reserved for future use)
189	  x3 = 0 (reserved for future use)
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