Documentation / devicetree / bindings / crypto / qcom-qce.yaml


Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm crypto engine driver

maintainers:
  - Bhupesh Sharma <bhupesh.sharma@linaro.org>

description:
  This document defines the binding for the QCE crypto
  controller found on Qualcomm parts.

properties:
  compatible:
    oneOf:
      - const: qcom,crypto-v5.1
        deprecated: true
        description: Kept only for ABI backward compatibility

      - const: qcom,crypto-v5.4
        deprecated: true
        description: Kept only for ABI backward compatibility

      - items:
          - enum:
              - qcom,ipq4019-qce
              - qcom,sm8150-qce
          - const: qcom,qce

      - items:
          - enum:
              - qcom,ipq6018-qce
              - qcom,ipq8074-qce
              - qcom,ipq9574-qce
              - qcom,msm8996-qce
              - qcom,qcm2290-qce
              - qcom,sdm845-qce
              - qcom,sm6115-qce
          - const: qcom,ipq4019-qce
          - const: qcom,qce

      - items:
          - enum:
              - qcom,sc7280-qce
              - qcom,sm8250-qce
              - qcom,sm8350-qce
              - qcom,sm8450-qce
              - qcom,sm8550-qce
              - qcom,sm8650-qce
          - const: qcom,sm8150-qce
          - const: qcom,qce

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

  iommus:
    minItems: 1
    maxItems: 8
    description:
      phandle to apps_smmu node with sid mask.

  interconnects:
    maxItems: 1
    description:
      Interconnect path between qce crypto and main memory.

  interconnect-names:
    const: memory

  dmas:
    items:
      - description: DMA specifiers for rx dma channel.
      - description: DMA specifiers for tx dma channel.

  dma-names:
    items:
      - const: rx
      - const: tx

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,crypto-v5.1
              - qcom,crypto-v5.4
              - qcom,ipq6018-qce
              - qcom,ipq8074-qce
              - qcom,ipq9574-qce
              - qcom,msm8996-qce
              - qcom,sdm845-qce
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: iface
            - const: bus
            - const: core
      required:
        - clocks
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,qcm2290-qce
              - qcom,sm6115-qce
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: core
      required:
        - clocks
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8150-qce
    then:
      properties:
        clocks: false
        clock-names: false

required:
  - compatible
  - reg
  - dmas
  - dma-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-apq8084.h>
    crypto-engine@fd45a000 {
        compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
        reg = <0xfd45a000 0x6000>;
        clocks = <&gcc GCC_CE2_AHB_CLK>,
                 <&gcc GCC_CE2_AXI_CLK>,
                 <&gcc GCC_CE2_CLK>;
        clock-names = "iface", "bus", "core";
        dmas = <&cryptobam 2>, <&cryptobam 3>;
        dma-names = "rx", "tx";
        iommus = <&apps_smmu 0x584 0x0011>,
                 <&apps_smmu 0x586 0x0011>,
                 <&apps_smmu 0x594 0x0011>,
                 <&apps_smmu 0x596 0x0011>;
    };