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Documentation / devicetree / bindings / i2c / i2c-at91.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:45 EST.

1	I2C for Atmel platforms
2	
3	Required properties :
4	- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5	     "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
6	     "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
7	- reg: physical base address of the controller and length of memory mapped
8	     region.
9	- interrupts: interrupt number to the cpu.
10	- #address-cells = <1>;
11	- #size-cells = <0>;
12	- clocks: phandles to input clocks.
13	
14	Optional properties:
15	- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
16	- dmas: A list of two dma specifiers, one for each entry in dma-names.
17	- dma-names: should contain "tx" and "rx".
18	- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
19	  capable I2C controllers.
20	- Child nodes conforming to i2c bus binding
21	
22	Examples :
23	
24	i2c0: i2c@fff84000 {
25		compatible = "atmel,at91sam9g20-i2c";
26		reg = <0xfff84000 0x100>;
27		interrupts = <12 4 6>;
28		#address-cells = <1>;
29		#size-cells = <0>;
30		clocks = <&twi0_clk>;
31		clock-frequency = <400000>;
32	
33		24c512@50 {
34			compatible = "24c512";
35			reg = <0x50>;
36			pagesize = <128>;
37		}
38	}
39	
40	i2c0: i2c@f8034600 {
41		compatible = "atmel,sama5d2-i2c";
42		reg = <0xf8034600 0x100>;
43		interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
44		dmas = <&dma0
45			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
46			AT91_XDMAC_DT_PERID(11)>,
47		       <&dma0
48			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
49			AT91_XDMAC_DT_PERID(12)>;
50		dma-names = "tx", "rx";
51		#address-cells = <1>;
52		#size-cells = <0>;
53		clocks = <&flx0>;
54		atmel,fifo-size = <16>;
55	
56		wm8731: wm8731@1a {
57			compatible = "wm8731";
58			reg = <0x1a>;
59		};
60	};
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