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Based on kernel version 4.7.2. Page generated on 2016-08-22 22:42 EST.

1	Atmel NAND flash
2	
3	Required properties:
4	- compatible: The possible values are:
5		"atmel,at91rm9200-nand"
6		"atmel,sama5d2-nand"
7		"atmel,sama5d4-nand"
8	- reg : should specify localbus address and size used for the chip,
9		and hardware ECC controller if available.
10		If the hardware ECC is PMECC, it should contain address and size for
11		PMECC and PMECC Error Location controller.
12		The PMECC lookup table address and size in ROM is optional. If not
13		specified, driver will build it in runtime.
14	- atmel,nand-addr-offset : offset for the address latch.
15	- atmel,nand-cmd-offset : offset for the command latch.
16	- #address-cells, #size-cells : Must be present if the device has sub-nodes
17	  representing partitions.
18	
19	- gpios : specifies the gpio pins to control the NAND device. detect is an
20	  optional gpio and may be set to 0 if not present.
21	
22	Optional properties:
23	- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
24	- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
25	  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
26	  "soft_bch".
27	- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
28	  capable of BCH encoding and decoding, on devices where it is present.
29	- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
30	  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
31	  is "atmel,sama5d2-nand", 32 is also valid.
32	- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
33	  are: 512, 1024.
34	- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
35	  for different sector size. First one is for sector size 512, the next is for
36	  sector size 1024. If not specified, driver will build the table in runtime.
37	- nand-bus-width : 8 or 16 bus width if not present 8
38	- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
39	
40	Nand Flash Controller(NFC) is an optional sub-node
41	Required properties:
42	- compatible : "atmel,sama5d3-nfc".
43	- reg : should specify the address and size used for NFC command registers,
44	        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
45	        if don't want to use it.
46	- clocks: phandle to the peripheral clock
47	Optional properties:
48	- atmel,write-by-sram: boolean to enable NFC write by SRAM.
49	
50	Examples:
51	nand0: nand@40000000,0 {
52		compatible = "atmel,at91rm9200-nand";
53		#address-cells = <1>;
54		#size-cells = <1>;
55		reg = <0x40000000 0x10000000
56		       0xffffe800 0x200
57		      >;
58		atmel,nand-addr-offset = <21>;	/* ale */
59		atmel,nand-cmd-offset = <22>;	/* cle */
60		nand-on-flash-bbt;
61		nand-ecc-mode = "soft";
62		gpios = <&pioC 13 0	/* rdy */
63			 &pioC 14 0 	/* nce */
64			 0		/* cd */
65			>;
66		partition@0 {
67			...
68		};
69	};
70	
71	/* for PMECC supported chips */
72	nand0: nand@40000000 {
73		compatible = "atmel,at91rm9200-nand";
74		#address-cells = <1>;
75		#size-cells = <1>;
76		reg = < 0x40000000 0x10000000	/* bus addr & size */
77			0xffffe000 0x00000600	/* PMECC addr & size */
78			0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
79			0x00100000 0x00100000	/* ROM addr & size */
80			>;
81		atmel,nand-addr-offset = <21>;	/* ale */
82		atmel,nand-cmd-offset = <22>;	/* cle */
83		nand-on-flash-bbt;
84		nand-ecc-mode = "hw";
85		atmel,has-pmecc;	/* enable PMECC */
86		atmel,pmecc-cap = <2>;
87		atmel,pmecc-sector-size = <512>;
88		atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
89		gpios = <&pioD 5 0	/* rdy */
90			 &pioD 4 0	/* nce */
91			 0		/* cd */
92			>;
93		partition@0 {
94			...
95		};
96	};
97	
98	/* for NFC supported chips */
99	nand0: nand@40000000 {
100		compatible = "atmel,at91rm9200-nand";
101		#address-cells = <1>;
102		#size-cells = <1>;
103		ranges;
104	        ...
105	        nfc@70000000 {
106			compatible = "atmel,sama5d3-nfc";
107			#address-cells = <1>;
108			#size-cells = <1>;
109			clocks = <&hsmc_clk>
110			reg = <
111				0x70000000 0x10000000	/* NFC Command Registers */
112				0xffffc000 0x00000070	/* NFC HSMC regs */
113				0x00200000 0x00100000	/* NFC SRAM banks */
114			>;
115		};
116	};
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