# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Thunder Bay pin controller

maintainers:
  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>

description: |
  Intel Thunder Bay SoC integrates a pin controller which enables control
  of pin directions, input/output values and configuration
  for a total of 67 pins.

properties:
  compatible:
    const: intel,thunderbay-pinctrl

  reg:
    maxItems: 1

  gpio-controller: true
 
  '#gpio-cells':
    const: 2

  gpio-ranges:
    maxItems: 1

  interrupts:
    description:
      Specifies the interrupt lines to be used by the controller.
    maxItems: 2

  interrupt-controller: true
 
  '#interrupt-cells':
    const: 2

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object
    additionalProperties: false

    description:
      Child nodes can be specified to contain pin configuration information,
      which can then be utilized by pinctrl client devices.
      The following properties are supported.

    properties:
      pins:
        description: |
          The name(s) of the pins to be configured in the child node.
          Supported pin names are "GPIO0" up to "GPIO66".

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength:
        description: Drive strength for the pad.
        enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]

      bias-bus-hold:
        type: boolean

      input-schmitt-enable:
        type: boolean

      slew-rate:
        description: GPIO slew rate control.
                      0 - Slow
                      1 - Fast
        enum: [0, 1]

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    // Example 1
    pinctrl0: gpio@0 {
        compatible = "intel,thunderbay-pinctrl";
        reg = <0x600b0000 0x88>;
        gpio-controller;
        #gpio-cells = <0x2>;
        gpio-ranges = <&pinctrl0 0 0 67>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };
 
    // Example 2
    pinctrl1: gpio@1 {
        compatible = "intel,thunderbay-pinctrl";
        reg = <0x600c0000 0x88>;
        gpio-controller;
        #gpio-cells = <0x2>;
        gpio-ranges = <&pinctrl1 0 0 53>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };