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Documentation / devicetree / bindings / spi / spi-davinci.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:47 EST.

1	Davinci SPI controller device bindings
2	
3	Links on DM:
4	Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5	dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6	OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
7	
8	Required properties:
9	- #address-cells: number of cells required to define a chip select
10		address on the SPI bus. Should be set to 1.
11	- #size-cells: should be zero.
12	- compatible:
13		- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14		- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15		- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
16			family
17	- reg: Offset and length of SPI controller register space
18	- num-cs: Number of chip selects. This includes internal as well as
19		GPIO chip selects.
20	- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
21		IP to the interrupt controller within the SoC. Possible values
22		are 0 and 1. Manual says one of the two possible interrupt
23		lines can be tied to the interrupt controller. Set this
24		based on a specifc SoC configuration.
25	- interrupts: interrupt number mapped to CPU.
26	- clocks: spi clk phandle
27	
28	Optional:
29	- cs-gpios: gpio chip selects
30		For example to have 3 internal CS and 2 GPIO CS, user could define
31		cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
32		where first three are internal CS and last two are GPIO CS.
33	
34	Optional properties for slave devices:
35	SPI slave nodes can contain the following properties.
36	Not all SPI Peripherals from Texas Instruments support this.
37	Please check SPI peripheral documentation for a device before using these.
38	
39	- ti,spi-wdelay : delay between transmission of words
40		(SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
41		clock periods.
42	
43		delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
44	
45	Below is timing diagram which shows functional meaning of
46	"ti,spi-wdelay" parameter.
47	
48	             +-+ +-+ +-+ +-+ +-+                           +-+ +-+ +-+
49	SPI_CLK      | | | | | | | | | |                           | | | | | |
50	  +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
51	
52	SPI_SOMI/SIMO+-----------------+                           +-----------
53	  +----------+ word1           +---------------------------+word2
54	             +-----------------+                           +-----------
55	                                          WDELAY
56	                                <-------------------------->
57	
58	Example of a NOR flash slave device (n25q032) connected to DaVinci
59	SPI controller device over the SPI bus.
60	
61	spi0:spi@20BF0000 {
62		#address-cells			= <1>;
63		#size-cells			= <0>;
64		compatible			= "ti,dm6446-spi";
65		reg				= <0x20BF0000 0x1000>;
66		num-cs				= <4>;
67		ti,davinci-spi-intr-line	= <0>;
68		interrupts			= <338>;
69		clocks				= <&clkspi>;
70	
71		flash: n25q032@0 {
72			#address-cells = <1>;
73			#size-cells = <1>;
74			compatible = "st,m25p32";
75			spi-max-frequency = <25000000>;
76			reg = <0>;
77			ti,spi-wdelay = <8>;
78	
79			partition@0 {
80				label = "u-boot-spl";
81				reg = <0x0 0x80000>;
82				read-only;
83			};
84	
85			partition@1 {
86				label = "test";
87				reg = <0x80000 0x380000>;
88			};
89		};
90	};
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