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Documentation / powerpc / dts-bindings / spi-bus.txt


Based on kernel version 2.6.37. Page generated on 2011-03-22 21:57 EST.

1	SPI (Serial Peripheral Interface) busses
2	
3	SPI busses can be described with a node for the SPI master device
4	and a set of child nodes for each SPI slave on the bus.  For this
5	discussion, it is assumed that the system's SPI controller is in
6	SPI master mode.  This binding does not describe SPI controllers
7	in slave mode.
8	
9	The SPI master node requires the following properties:
10	- #address-cells  - number of cells required to define a chip select
11	    		address on the SPI bus.
12	- #size-cells     - should be zero.
13	- compatible      - name of SPI bus controller following generic names
14	    		recommended practice.
15	No other properties are required in the SPI bus node.  It is assumed
16	that a driver for an SPI bus device will understand that it is an SPI bus.
17	However, the binding does not attempt to define the specific method for
18	assigning chip select numbers.  Since SPI chip select configuration is
19	flexible and non-standardized, it is left out of this binding with the
20	assumption that board specific platform code will be used to manage
21	chip selects.  Individual drivers can define additional properties to
22	support describing the chip select layout.
23	
24	SPI slave nodes must be children of the SPI master node and can
25	contain the following properties.
26	- reg             - (required) chip select address of device.
27	- compatible      - (required) name of SPI device following generic names
28	    		recommended practice
29	- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
30	- spi-cpol        - (optional) Empty property indicating device requires
31	    		inverse clock polarity (CPOL) mode
32	- spi-cpha        - (optional) Empty property indicating device requires
33	    		shifted clock phase (CPHA) mode
34	- spi-cs-high     - (optional) Empty property indicating device requires
35	    		chip select active high
36	
37	SPI example for an MPC5200 SPI bus:
38		spi@f00 {
39			#address-cells = <1>;
40			#size-cells = <0>;
41			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
42			reg = <0xf00 0x20>;
43			interrupts = <2 13 0 2 14 0>;
44			interrupt-parent = <&mpc5200_pic>;
45	
46			ethernet-switch@0 {
47				compatible = "micrel,ks8995m";
48				spi-max-frequency = <1000000>;
49				reg = <0>;
50			};
51	
52			codec@1 {
53				compatible = "ti,tlv320aic26";
54				spi-max-frequency = <100000>;
55				reg = <1>;
56			};
57		};
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